Data storage cell with transistors operating at different thresh

Details Data storage cell with transistors operating at different thresh Data storage cell with transistors operating at different thresh

1975-12-16

1977-02-01

Fears, Terrell W.

Communications: electrical

Digital comparator systems

340173FF, 307238, 307279, G11C 1140

Patent

active

040064697

ABSTRACT:
A semiconductor memory or storage circuit includes cross coupled transistors and isolating transistors operating at a first threshold voltage and load transistors for the cross coupled transistors operating at a second threshold voltage. The storage cell is disposed in a matrix of word and bit lines. The load devices are connected between a supply voltage and the cross coupled transistors which are returned to a reference potential. The isolating transistors are connected between the cross coupled transistors and adjacent bit lines. The word line is connected to the gates of both the isolating transistors and the load devices. When the word line is down, the isolating transistors are turned off and the load devices supply sufficient current to retain the stored information in the cross coupled transistors. When the word line is raised, the gate voltage of the load transistors is raised to supply additional current to the circuit. Simultaneously, the isolating transistors connect the circuit to the bit lines for Read/Write modes of operation. The invention achieves cell powering without a pulse power gate terminal. Also, the invention does not require a special deselect potential to keep current in the circuit during the storage mode.

REFERENCES:
patent: 3949382 (1976-04-01), Yasui
patent: 3959781 (1976-05-01), Mehta

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