Data steering logic for the output of a cache memory having an o

Details Data steering logic for the output of a cache memory having an o Data steering logic for the output of a cache memory having an o

1980-12-31

1984-04-24

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 1300

Patent

active

044451725

ABSTRACT:
A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

REFERENCES:
patent: 4005389 (1977-01-01), Penzel
patent: 4133028 (1979-01-01), Berstein
patent: 4135242 (1979-01-01), Ward et al.
patent: 4189768 (1980-02-01), Liptay et al.
patent: 4189770 (1980-02-01), Gannon et al.
patent: 4225922 (1980-09-01), Porter
patent: 4245307 (1981-01-01), Kapeghian et al.
patent: 4251864 (1981-02-01), Kindell et al.
patent: 4285039 (1981-08-01), Patterson et al.
patent: 4378591 (1983-03-01), Lemay

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