Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2001-02-01
2002-06-25
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06411980
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data split parallel shifter for splitting data in connection with a processing of a microprocessor and then executing a shifting operation. Further, the present invention relates to an adder/subtractor and, more particularly, an adder/subtractor employed in a processor for supporting mainly multimedia functions, etc.
2. Description of the Prior Art
In a processor module of a processor for executing data processing, as an approach for improving a data processing efficiency, there is a processing system in which data are split into a plurality of fields and then data in respective fields are processed in bulk. For example, 64-bit data is split into four 16-bit data and then four adding operations are executed at the same time according to an add command.
A
[
63
:
48
]
A
[
47
:
32
]
A
[
31
:
16
]
A
[
15
:
0
]
+
+
+
+
B
[
63
:
48
]
B
[
47
:
32
]
B
[
31
:
16
]
B
[
15
:
0
]
=
=
=
=
C
[
63
:
48
]
C
[
47
:
32
]
C
[
31
:
16
]
C
[
15
:
0
]
This processing system can show its performance in the fields such as image processing, speech processing, etc. rather than existing scientific and technical computation, business processing computation, etc. These processings need a shifting process in addition to the arithmetic operations and the logical operation. Normally, as the shifting process, there are the logical shift in which 0 is filled in vacant locations caused by shift, and the arithmetic shift which executes the code extension. In order to enable the shifting process after the data is split into a plurality of fields, a switching process indicating which portion of the fields should be code-extended in conformity with split mode is requested. For example, the results derived when a 3-bit rightward arithmetic shift is applied to 32-Bit data in a 32 bit mode, a 16 bit×2 mode, and an 8 bit×4 mode respectively are given in the following.
bit 31
bit 0
Original data
110 11011
001 10101
001 00100
100 10100
32 bit mode
111
11011
011 00110
101 00100
100 10010
16 bit × 2 mode
111
11011
011 00110
000
00100
100 10010
8 bit × 4 mode
111
11011
000
00110
000
00100
111
10010
Out of the above data, underlined portions are code extension portions. That is, the code extension is applied to the bit
31
in the 32-bit shift mode. In the 16 bit×2 mode, the code extension is applied to the bit
31
in upper 16 bits, while the code extension is applied to the bit
15
in lower 16 bits. In the 8 bit×4 mode, the bit
31
is extended in the bit range from the bit
31
to the bit
24
, the bit
23
is extended in the bit range from the bit
23
to the bit
16
, the bit
15
is extended in the bit range from the bit
15
to the bit
8
, and the bit
7
is extended in the bit range from the bit
7
to the bit
0
. In the logical shift, the above underlined portions are extended into 0.
Next, a configuration of the shifter will be explained hereunder. For clarification of explanation, the rightward shifting process will be explained.
To begin with, the normal shifter without a split function will be explained. A normal 32-bit rightward shifter is shown in FIG.
1
. In
FIG. 1
, in the 32-bit shifter, bit shifters
101
to
105
for shifting the data by 1 bit, 2 bit, 4 bit, 8 bit, and 16 bit respectively are connected in a multistage fashion. Such bit shifters are constructed by a simple selector respectively. The 32-bit shifter is constructed by stacking these selectors in a multistage fashion. The 1-bit shifter
101
outputs data, which is located at the bit adjacent to the corresponding bit on the left side by one bit, out of the data supplied from the 2-bit shifter
102
when the shifting is executed, while the 1-bit shifter
101
outputs data located at the corresponding bit as it is when the shifting is not executed. A select signal indicating whether adjacent data should be output or the data should be output as it is can be generated based on the least significant bit of the signal indicating an amount of shift and the signal indicating the leftward/rightward shifting direction. More particularly, the 1-bit shifting is executed if 1 is set at the least significant bit, while the 1-bit shifting is not needed if 0 is set at the least significant bit and thus the data is output downward as it is. In the 2-bit shifter
102
, either the data located on the left side by two bits in relation to the corresponding bit should be output or the data located at the corresponding bit should be output as it is can be selected. The select signal for the 2-bit shifter
102
is a value on the second least significant bit in the signal indicating the amount of shift. Depending upon that which shifters are to be operated in compliance with the amount-of-shift signal respectively, the shifting operation to achieve any amount of shift ranging from the 0 bit to 31 bit can be carried out. For instance, in the case of the 3-bit shifting, shift of the data is effected by the 1-bit shifter
101
and 2-bit shifter
102
, nevertheless no shift of the data is effected by other shifters
103
,
104
,
105
.
Unless the data is split into the fields, the code extension process can be implemented by extending either the leftmost value of the original data, if the arithmetic shift is applied, or 0, if the logical shift is applied, by the bit number equal to the amount of shift from the most significant bit in respective shifters.
The data used in code extension consists of a control signal indicating which one of the arithmetic shift and the logical shift should be executed and actual code extension data, and such data can be generated previously in a code extension data generator. For example, there is no lefthand data to be fetched for the leftmost selector in the 1-bit shifter
101
. However, if the code extension data supplied from the code extension data generator is inserted into the port, such leftmost selector can output the code extension data when one-bit shift is generated.
As shown in
FIG. 2
, the code extension data generator is constructed to comprise multiplexers
106
to
108
and logic gates
109
to
112
, for example. In the arithmetic shift in which an arithmetic shift signal is at a high level, according to such configuration, the bit
31
of the original data is output as the code extension data for all 32 bits in the 32-bit shift mode. Then, in the 16 bit×2 mode, the bit
31
of the original data is output in the bit range of the upper bits
31
to
16
while the bit
15
of the original data is output in the bit range of the lower bits
15
to
0
. Then, in the 8 bit×4 mode, the bit
31
of the original data is output in the bit range of the bits
31
to
24
, the bit
23
of the original data is output in the bit range of the bits
23
to
16
, the bit
15
of the original data is output in the bit range of the bits
15
to
8
, and the bit
7
of the original data is output in the bit range of the bits
7
to
0
. On the contrary, in the logical shift in which the arithmetic shift signal is at a low level, 0 is output to all bits as the code extension data.
In the event that the 16 bit×2 mode and the 8 bit×4 mode, described above, are added to the shifter shown in
FIG. 1
, it becomes an issue how the above code extension process should be carried out. As shown in
FIG. 3
, in order to add the code extension function, code extension selectors
113
for selecting either the code extension or the normal shift can be inserted between respective stages of the shifters
101
to
105
respectively.
In the 16 bit×2 mode, the 16-bit shifter
105
controls all code extension selectors
113
to select the code extension. In the 8-bit shifter
104
, the code extension selector
113
controls to select the code extension for the bits
15
to
8
. Similarly, the 4-bit shifter
103
con
Foley & Lardner
Kabushiki Kaisha Toshiba
Malzahn David H.
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