Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2000-05-09
2004-12-14
Ingberg, Todd (Department: 2122)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C712S241000
Reexamination Certificate
active
06832370
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and method for using a compiler in a computer system to perform data speculation within modulo scheduled loops.
BACKGROUND OF THE INVENTION
In software program compilers, it is desirable to increase the efficiency of the compiler. Two different methods of optimizing compiler performance include data speculation and use of a modulo scheduler. However, these methods operate independent of one another and thus do not gain the benefit of combining them. In particular, in the absence of a solution such as the data speculation, the modulo scheduler must make conservative assumptions with respect to memory dependencies, which reduces the efficiency of the scheduled code.
On the other hand, in the absence of modulo scheduling, data speculation within loops must rely upon techniques such as unrolling with acyclic scheduling to exploit instruction-level parallelism (ILP) across iterations. With this technique, however, the unroll factor required to achieve the same amount of overlap as modulo scheduling is difficult to determine. Also, unrolling can have undesirable side effects such excessive code expansion and negative cache performance.
Accordingly, a need exists for an apparatus method to perform data speculation within modulo scheduled loops.
SUMMARY OF THE INVENTION
An apparatus and method consistent with the present invention schedule instructions in a compiler. They include receiving instructions for scheduling along with data speculation code. They also include locating a schedule for specifying an order of execution of the instructions, generating recovery code for the data speculation code, and allocating rotating registers related to the scheduling of the instructions for execution and related to the recovery code. Based upon the locating and allocating, an initiation interval is determined specifying a number of instruction issue cycles between initiation of successive iterations related to the scheduling of the instructions.
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Vinod Kathail, et al., “HPL-PD Architecture Specification: Version 1.1,” Feb. 2000, Hewlett-Packard Co., HPL-93-80 (R.1), pp. 1-58.*
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Ju Dz-ching
Nomura Kevin
Srinivasan Uma
Hewlett-Packard Development L.P.
Ingberg Todd
Kiss Eric B.
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