1995-09-29
1998-10-13
Downs, Robert W.
G06E 1518
Patent
active
058224971
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device, and has as an object thereof to provide a high performance semiconductor integrated circuit which is capable of ordering a plurality of inputted data by numerical size, that is to say, is capable of conducting high speed sorting, using hardware.
BACKGROUND ART
In the fields of information processing and automatic control, the comparison and discrimination by size of data expressed as numerical values plays an extremely important role.
For example, this includes determining the larger of two numbers, selecting a number of values in order of size from among a plurality of inputted data, and the rearrangement of a plurality of data in order of numerical size, that is to say, sorting, and the like.
Such operations can normally be conducted using a calculator; however, because a large number of operations are required, time is required, and it is extremely difficult to employ real-time control. In particular, in the case of use in the control of robots or the like, because it is necessary to attach the calculator to the robot and conduct calculations, realization by means of small LSI chips is required.
When attempts are made to employ microprocessors and to conduct these operations by means of the programming thereof, enormous amounts of time are required, and application is essentially impossible. Research and development has thus been conducted in order to produce circuits which conduct direct sorting by means of hardware; however, in order to realize such circuits, a large number of elements are necessary, and since operations are conducted through circuits having a number of stages, LSI which is small in scale and capable of high speed operation has not been realized.
The present invention has as an object thereof to provide a semiconductor device which is capable of conducting operations making a size comparison of a plurality of data at high speed, and ordering these data according to size, using simple circuitry.
DISCLOSURE OF THE INVENTION
The present invention is a semiconductor device constructed using one or more neuron MOS transistors having a semiconducting region of one conductivity type on a substrate, having source and drain regions of an opposite conductivity type provided within this region, having a floating gate electrode in a potentially floating state which is provided via an insulating film on the region isolating said source and drain regions, and having a plurality of input gate electrodes capacitively coupled with the floating gate electrode via an insulating film, characterized in being provided with: an inverter circuit group including two or more inverter circuits formed by neuron MOS transistors; a means for applying a first signal voltage common to the two or more inverters of the inverter circuit group to a first input gate of the inverter circuits; a means for applying a given second signal voltage to one or more second input gates other than the first input gate of the inverter circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the inverter circuits of the inverter circuit group with a time delay generated using the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals in accordance with the ON and OFF of the transistor; a means for executing a given logical operation with respect to the output voltage signals generated by the inverter circuit group; and a function of storing the result of the logical operation in the storage circuits.
BRIEF DESCRIPTION OF THE DIAGRAMS
FIG. 1 is a circuit diagram showing a first embodiment.
FIG. 2 is a circuit diagram of the .nu.MOS of embodiment 1.
FIG. 3 is a circuit diagram showing a modification of embodiment 1.
FIG. 4 is an example of the cross sectional structure of a four-input N-channel .nu.MOS transistor (N-.nu.MOS).
FIG. 5 is a simpl
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Ohmi Tadahiro
Shibata Tadashi
Yamashita Takeo
Downs Robert W.
Shah Sanjiv
Tadashi Shibata and Tadahiro OHMI
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