Pulse or digital communications – Receivers
Reexamination Certificate
1999-01-06
2003-08-19
Deppe, Betsy L. (Department: 2634)
Pulse or digital communications
Receivers
C375S340000, C375S376000, C375S377000
Reexamination Certificate
active
06608871
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data slicers.
A phase detector described in this application is the subject of UK Patent Application No. 9800353.6.
BACKGROUND OF THE INVENTION
To recover data from noisy channels, such as for example magnetic data carriers having high data densities, it is known to class the write/read channel of the data carrier in accordance with a partial response characteristic which approximates to the frequency response characteristics of the channel, and select the arrangement or design of a digital data recovery circuit to optimize data recovery from a channel with that partial response characteristic. As the correct recovery of data is so dependent on how well the channel characteristics are matched by the form of data recovery circuit selected, it is common to provide an equalizer circuit on the input of the data recovery circuit to compensate for any difference between the actual and the approximated channel characteristics.
The data recovery circuit contains a phase-lock loop circuit arrangement which receives an analog read signal, from the equalizer circuit if there is one, and operates to control an oscillator at the phase and an integer multiple frequency of components of interest of the incoming data stream. Signals generated by this oscillator are used to sample the incoming analog signal at appropriate sampling points, from which samples data recovery is performed. Correct phase alignment of the oscillator signals and the components of interest of the analog read signal are critical in performing correct data recovery.
To assist the phase lock loop circuit arrangement in achieving fast initial frequency and phase alignment, the data carrier will usually have one or more regions in which VFO field data has been intentionally written. The VFO field data is a regular data pattern which, when being read, provides an analog signal which in approximately sinusoidal and periodic in nature. In using these data channels, it is known for the data to be encoded to contain a minimum of two consecutive like bits in the data stream, and the VFO field data may for example comprise a succession of pairs of like data bits.
It is widely appreciated that certain types of optical data carrier channels currently being investigated for development will have a response characteristic approximating that of equation (1).
F
(
D
)=
a+bD+bD
2
+aD
3
Eqn. (1)
Here, a and b are constant coefficients and D is a unit delay operator. This type of channel can be referred to as a class of partial response PR(a, b, b, a) channel.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data slicer comprises means to use knowledge of the value of an input signal received on at least one clock cycle preceding a current clock cycle to estimate where in the period of a read signal a present sample value relates to, and means to provide an output signal using extrapolation of the preceding values.
In accordance with a second aspect of the present invention, a data slicer comprises:
ideal signal level determining means for determining an ideal signal level which most closely corresponds to the signal level of an input signal at a sampling point;
state means for providing a plurality of states each state corresponding to a sampling point in the period of the input signal and each state having associated therewith an ideal signal level;
state determining means for determining the initial state of the state means in response to the determined ideal signal level, and means thereafter to step the state means sequentially through the plurality of states at the sampling rate, the ideal signal level corresponding to the current state being provided as an output signal.
Preferably the state determining means determines the initial state in response also to an ideal signal level determined for a preceding sampling point.
REFERENCES:
patent: 5412692 (1995-05-01), Uchida
patent: 5469091 (1995-11-01), Takahashi et al.
patent: 5572558 (1996-11-01), Beherns
patent: 6246723 (2001-06-01), Bliss et al.
patent: WO 93/19547 (1993-09-01), None
patent: WO 93/26110 (1993-12-01), None
Popplewell Andrew
Williams Stephen
Deppe Betsy L.
LSI Logic Corporation
Maiorana P.C. Christopher P.
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