Data slicer circuit

Details Data slicer circuit Data slicer circuit

2001-08-01

2004-05-11

Lee, Michael H. (Department: 2614)

Television

Nonpictorial data packet in television format

Data separation or detection

C348S468000, C327S094000, C375S340000

Reexamination Certificate

active

06734918

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a data slicer circuit that slices various data services multiplexed on a video signal.
BACKGROUND OF THE INVENTION
In character multiplex broadcasting, such as closed caption (CC) service, in a vertical blanking interval of a television video signal, digital data in a data packet form is multiplexed. Since the waveform of a multiplexed signal has a binary NRZ (Non-Return-to-Zero) form using pulses, a receiver of the character multiplex broadcasting has to convert the binary NRZ pulses to simple pluses having high and low levels. The receiver therefore has a data slicer circuit for extracting such multiplexed binary NRZ pulses from a television video signal and decoding the pulses to digital data such as character data.
FIG. 8
is a block diagram showing a schematic configuration of a conventional data slicer circuit. This conventional data slicer circuit has the capacitor C
10
that receives a television video signal, the clamping circuit
110
having an input terminal connected to the output of the capacitor C
10
. That is, the clamping circuit
110
receives the video signal by capacitive coupling.
The data slicer circuit also has the differential amplifier
120
having a non-inversion input terminal and an inversion input terminal. Output of the clamping circuit
110
is supplied to the non-inversion input terminal of the differential amplifier
120
. Furthermore, output of the clamping circuit
110
is also supplied to the switch SW
10
. Output of the switch SW
10
is supplied to the inversion input terminal of the differential amplifier
120
. Furthermore, output of the switch SW
10
is also supplied to the capacitor C
11
. Output of this capacitor C
11
is grounded.
The conventional data slicer circuit operates as follows. FIG.
9
A and
FIG. 9B
are timing charts for explaining the operation of the conventional data slicer circuit. A video signal capable of obtaining CC service will be described as an example. In the CC service, a signal synchronized at 503 kHz is multiplexed on line
21
in the vertical blanking interval of the video signal. As shown in
FIG. 9A
, if the service data is multiplexed on the line
21
in the vertical blanking interval of the video signal, after its synchronization signal, a clock run-in signal is multiplexed and, further, code data constructed by a framing code indicative of the start of service data and information data indicative of service contents follows the clock run-in signal.
The data slicer circuit first clamps the video signal to a pedestal potential with the clamping circuit
110
and detects the synchronization signal. After that, the data slicer circuit generates a timing signal TS, shown in
FIG. 9B
, in the clock run-in period and turns the switch SW
1
O on with the timing signal TS. When the switch SW
10
turns ON, the capacitor C
11
(dotted line in
FIG. 9A
) is charged with the clock run-in signal, thereby supplying a potential obtained by smoothing the clock run-in signal to the inversion input terminal of the differential amplifier
120
. On the other hand, the clamped video signal is input to the non-inversion input terminal of the differential amplifier
120
.
The differential amplifier
120
therefore outputs a signal obtained by slicing the video signal by the average potential of the clock run-in signal. In other words, the differential amplifier
120
slices a signal existing in the code data period by using the average potential of the clock run-in signal as a decode potential and outputs resultant data indicative of service information.
In the conventional data slicer circuit, irrespective of whether the clock run-in signal is multiplexed or not, the smoothing operation is always performed by the capacitor C
11
when the switch SW
10
is turned on in response to the timing signal TS. However, there is consequently a problem in the conventional data slicer circuit that, even if the clock run-in signal is not multiplexed, the potential of the signal in this case is applied to one end of the capacitor C
11
and, as a result, the capacitor C
11
is discharged. In other words, due to the discharge, the decode potential decreases, and a problem such that a normal decoding process cannot be performed occurs.
As service realized by multiplexing another signal on the video signal, except for the CC service, other services such as ID-1 service (EIAJ, CPX-1204) are known. Particularly, a signal for the CC service is multiplexed as data having an amplitude of 50IRE on the line
21
in the vertical blanking interval. A signal for the ID-1 service is multiplexed as data having an amplitude of 70IRE on line
20
in the vertical blanking interval. These different services can be therefore provided by using the same television video signal.
In the conventional data slicer circuit, however, to simultaneously receive such different services, it is necessary to provide the capacitor C
11
for holding the decode potential and the differential amplifier
120
for each service.
SUMMARY OF THE INVENTION
It is an object of this invention to obtain a data slicer circuit capable of stabilizing a decode potential by detecting a clock run-in signal and receiving different services by common components.
The data slicer circuit according to one aspect of this invention comprises a holding unit which holds a pedestal potential of the video signal; an averaging/holding unit which calculates an average potential of signals existing in a period where a reference clock signal of said multiplex signal is present, and holds the calculated average potential; and a comparing unit which compares the potentials held by said averaging/holding unit and holding unit. The comparing unit outputs a detection signal indicative of the presence of the multiplex signal when the potential held by said averaging/holding unit is higher than the potential held by said holding unit.
Thus, the comparing unit can detect whether a multiplex signal of CC service or the like is multiplexed on the video signal. Consequently, a timing of holding a decode potential and the like can be known from the detection signal.
The data slicer circuit according to another aspect of this invention comprises an averaging/holding unit which calculates an average potential of signals existing in a period where a reference clock signal of said multiplex signal is present, and holds the calculated average potential; and a comparing unit which adds (a peak potential of the multiplex signal−pedestal potential of the video signal)/2 to the potential held by said averaging/holding unit to obtain a comparison potential, calculates a difference between a potential of the video signal and the comparison potential, counts the number of clocks based on the difference between the potential of the video signal and the comparison potential. The comparing unit outputs a detection signal indicative of the presence of the multiplex signal when the count reaches to a predetermined value.
Thus, the comparing unit counts the number of clocks of the reference clock signal in the multiplex signal of the CC service or the like on the video signal, and determines the presence/absence of the multiplex signal from the count.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 4115811 (1978-09-01), Goff
patent: 4358790 (1982-11-01), Summers
patent: 4613900 (1986-09-01), Matsunaga et al.
patent: 4667235 (1987-05-01), Nozoe et al.
patent: 5304866 (1994-04-01), Uranaka
patent: 5371545 (1994-12-01), Tults
patent: 5404172 (1995-04-01), Berman et al.
patent: 5412692 (1995-05-01), Uchida
patent: 5481212 (1996-01-01), Shima
patent: 5483289 (1996-01-01), Urade et al.
patent: 5596372 (1997-01-01), Berman et al.
patent: 5666167 (1997-09-01), Tults
patent: 5715011 (1998-02-01), Bramwell
patent: 5744985 (1998-04-01), Nishida
patent: 5754250 (1998-05-01), Cooper
patent: 5760844 (1998-06-01), Jorden
patent: 5801555 (1998-09-01), Kwon
patent: 5831562 (1998-11

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