Data signal responsive phase locked loop using averaging and ini

Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements

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331 17, 331 25, H03L 708

Patent

active

042465451

ABSTRACT:
A phase-locked loop oscillator system includes a phase comparator in the form of a flip flop which is switched between states in response to received data pulses at one input and oscillator generated clocking pulses at another input. The positive and negative outputs of the flip-flop energize positive and negative constant current generators whose outputs feed in parallel a low pass filter or integrator including a capacitor which is initially discharged at the start of data reception by a field effect transistor connected in parallel with the capacitor. The output of the filter is a voltage whose amplitude is a measure of the phase difference between the sets of pulses. This voltage controls the amplitude of charging current fed to a sawtooth waveform generator to control the frequency thereof. The output of the generator is processed to form the clocking pulses for the system.

REFERENCES:
patent: 3594655 (1971-07-01), Reisfeld
patent: 3599110 (1971-08-01), Gindi
patent: 3701039 (1972-10-01), Lang et al.
patent: 4003086 (1977-01-01), Larsen et al.

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