Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-03-23
2002-12-10
Hjerpe, Richard (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S099000, C345S100000, C345S101000, C345S102000, C345S103000, C345S104000, C345S211000, C345S213000
Reexamination Certificate
active
06492972
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data signal line driving circuit for continuously sampling input signals and outputting them, and an image display apparatus which adopts the data signal line driving circuit.
2. Description of the Related Art
Hereinafter, a liquid crystal display apparatus and a data line driving circuit used therein will be described using conventional examples of an image display apparatus and a data signal line driving circuit.
An active matrix type liquid crystal display apparatus is well known. This apparatus is composed of a pixel array ARRAY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD, as shown in FIG.
17
.
The pixel array ARY includes scanning signal lines GL and data signal lines SL crossing the scanning signal lines GL. Each pixel PIX is provided in a matrix in each portion surrounded by two adjacent scanning signal lines GL and two adjacent data signal lines SL.
The data signal line driving circuit SD sequentially samples input video signals DAT in synchronization with a timing signal such as a clock signal CLK
s
, and amplifies each sampled video signal, if required, to output it to each data signal line SL.
The scanning signal line driving circuit GD sequentially selects each scanning signal line GL in synchronization with a timing signal such as a clock signal CLK
g
, and controls opening and closing of each switching element in each pixel PIX along the selected scanning signal line GL, there by writing each video signal (data) output to each data signal line SL into each pixel PIX and allowing data written into each pixel PIX to be held.
As shown in
FIG. 18
, each pixel PIX shown in
FIG. 17
is composed of a field effect transistor SW which is a switching element and a pixel capacitance made of a liquid crystal capacitance CL and an auxiliary capacitance CS which is added if required.
As shown in
FIG. 18
, the data signal line SL is connected to one of electrodes of the pixel capacitance through a drain and a source of the transistor SW. A gate of the transistor SW is connected to the scanning signal electrode line GL, and the other electrode of the pixel capacitance is connected to a common electrode line of all the pixels. Due to a voltage applied to each liquid crystal capacitance CL, a transmittance or a reflectivity of liquid crystal is modulated, which contributes to a display.
Next, a method for sampling a video signal and outputting it to a data signal line will be described.
Examples of a method for driving a data signal line includes a dot sequential driving method and a line sequential driving method. Herein, only a dot sequential driving method will be described with reference to
FIGS. 19 and 20
. This description is also applicable to a line sequential driving method.
In each circuit shown in
FIGS. 19 and 20
, a shift register SR sequentially outputs sampling pulses while shifting them, in synchronization with a clock signal CLK (corresponding to the clock signal CLK
s
in FIG.
17
). Sampling pulses N
1
, N
2
, N
3
, and N
4
sequentially output from the shift register SR are sequentially supplied to respective analog switches G
1
, G
2
, G
3
, and G
4
. The analog switches G
1
, G
2
, G
3
, and G
4
sequentially open in response to the respective sampling pulses N
1
, N
2
, N
3
, and N
4
, sequentially sampling video signals transmitted to a video signal line DAT, and sequentially outputting respective sampled video signals SL
1
, SL
2
, SL
3
, and SL
4
.
In the shift register SR, unit circuits as shown in
FIG. 21
or
22
are arranged.
The unit circuit shown in
FIG. 21
forms the shift register SR which shifts pulses only in one direction, and is composed of two clock control inverter circuits
201
and one inverter circuit
202
.
The unit circuit shown in
FIG. 22
forms the shift register SR which shifts pulses in both directions, and is composed of two clock control inverter circuits
201
and two inverter circuits
203
.
Both the shift registers SR have a structure of a half-latch circuit, which latches a pulse only in one direction of a rising or falling of a clock signal and outputs a pulse width in one period of the clock signal.
In an example shown in
FIG. 19
, outputs of the shift register SR are directly used as the sampling pulses N
1
to N
4
. Therefore, the continuous sampling pulses overlap each other by a half as shown in FIG.
23
.
In an example shown in
FIG. 20
, respective overlapped portions of adjacent output pulses of the shift register SR are used as the sampling pulses N
1
to N
4
. Therefore, the continuous sampling pulses do not overlap each other as shown in FIG.
24
.
FIG. 25
shows an exemplary scanning signal line driving circuit. In this circuit, as shown in
FIG. 27
, a shift register SR sequentially outputs sampling pulses N
1
to N
4
while shifting them, in synchronization with a clock signal CLK corresponding to the clock signal CLK
g
in FIG.
17
. This driving circuit is designed in such a manner that adjacent output pulses of the shift register SR do not overlap each other. Furthermore, by selecting an overlapped portion between the signal thus obtained and a pulse width control signal GPS from outside, each sampling pulse having a desired pulse width is obtained.
In the conventional data signal line driving circuits shown in
FIGS. 19 and 20
, every other sampling pulse, N
1
to N
4
, partially overlaps with one another as shown in
FIG. 23
, and the continuous sampling pulses, N
1
to N
4
, partially overlap each other as shown in FIG.
24
. This is because, in the conventional circuit configuration, a sampling pulse rises when another sampling pulse falls. Furthermore, due to variation and the like in transistor characteristics in the circuit, a timing of a part of sampling pulses may be shifted. In this case, an overlapped portion of the respective sampling pulses becomes larger.
In the case where sampling pulses overlap each other, a level of a video signal to be written into a data signal line may be changed. For example, in the circuit shown in
FIG. 20
, when the subsequent sampling pulse N
3
rises before the sampling pulse N
2
is turned off as shown in
FIG. 26
, the video signal DAT is drawn to the data signal line SL
3
corresponding to the sampling pulse N
3
as well as the data signal line SL
2
corresponding to the sampling pulse N
2
. Therefore, a level of the video signal DAT to be output to the data signal line SL
2
decreases by &Dgr; V. Similarly, when the sampling pulse N
4
rises before the sampling pulse N
2
is turned off in the circuit shown in
FIG. 19
, the video signal DAT is drawn to two data signal lines SL
2
and SL
4
. Therefore, a level of the video signal DAT to be output to the data signal line SL
2
decreases.
Consequently, a desired pixel potential cannot be obtained, making it difficult to obtain a normal display. In particular, when there is a variation in an overlapped portion of sampling pulses, level change values of a video signal and a pixel potential vary, which may cause roughness and a stripe pattern in an image.
The circuit shown in
FIG. 25
has the following disadvantage: although a pulse width of each sampling pulse is adjusted, it is required to generate and supply the pulse width control signal GPS having a frequency twice that of the clock signal CLK; therefore, a burden on an external circuit is increased.
SUMMARY OF THE INVENTION
A data signal line driving circuit is provided, which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
In one embodiment of the present invention, each of the sampling signals is obtained as a NAND signal or a NOR
Kubota Yasushi
Sakai Tamotsu
Washio Hajime
Hjerpe Richard
Lesperance Jean
Sharp Kabushiki Kaisha
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