Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-04-15
2002-08-20
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S099000, C345S204000
Reexamination Certificate
active
06437768
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a data signal line driving circuit and an image display apparatus having a shift register circuit for transmitting a pulse signal in sync with a clock signal.
BACKGROUND OF THE INVENTION
A liquid crystal display device adopting an active matrix driving method has been known as an example image display apparatus. The liquid crystal display device adopting the above driving method is composed of a pixel array, a data signal line driving circuit, and a scanning signal line driving circuit.
A plurality of scanning signal lines and a plurality of data signal lines are provided in the pixel array to cross each other, and a pixel is provided to each area enclosed by two adjacent scanning signal lines and two adjacent data signal lines, thereby forming a matrix arrangement.
Each pixel is composed of, for example, an electric field effect transistor serving as a switching element, a liquid crystal capacitance, and an auxiliary capacitance. An image is displayed as transmittance of the liquid crystal in each pixel varies with the ON/OFF action of the electric field effect transistor at the timing of a signal supplied to the scanning signal lines, while a voltage is applied to the liquid crystal capacitance and auxiliary capacitance by a signal supplied to the data signal lines.
Incidentally, a conventional active matrix liquid crystal display device generally uses an amorphous silicon thin film formed over a transparent substrate as a substrate material for a pixel transistor, and the data signal line driving circuit and scanning signal line driving circuit are composed of outboard ICs.
In contrast, to meet an increasing demand for an upgraded drivability of the pixel transistor for a larger-scale screen, cost reduction for the driving IC packaging, or packaging reliability, there has been proposed a display apparatus in which the pixel array and driving circuits are formed monlithically out of a polycrystalline silicon thin film. To further upsize the screen and reduce the costs, it is also Proposed to make elements out of the polycrystalline silicon thin film formed over the glass substrate at a process temperature up to the glass distortion point (about 600° C.).
An example liquid crystal display device of the above monolithic structure includes a dielectric substrate having thereon formed the pixel array, data signal line driving circuit, and scanning signal line driving circuit.
Incidentally, the data signal line driving circuit has two driving methods: a dot sequential driving method and a line sequential driving method, and what distinguishes one method from the other is how a video signal is written into the data signal lines.
For example, as shown in
FIG. 15
, a data signal line driving circuit
122
adopting the dot sequential driving method is composed of a plurality of serially connected latch circuits LTi (i=1, 2, . . . , m), buffers BFi (i=1, 2, . . . , m) respectively connected to the output terminals of the latch circuits LTi, and analog switches ASi (i=1, 2, . . . , m) for sampling a data signal DAT from a video signal line.
The data signal DAT is inputted into the above-arranged data signal line driving circuit
122
through the video signal line as a video signal. Then, in the data signal line driving circuit
122
, each analog switch ASi is opened/closed in sync with a pulse signal outputted from the corresponding latch circuit LTi through the corresponding buffer BFi in sync with a clock signal CK and a start signal SP, whereby the data signal DAT supplied from the video signal line is sampled and written into the corresponding data signal line SLi (i=1, 2, . . . ,m).
Also, as shown in
FIG. 16
, in a scanning signal line driving circuit
123
, the output terminals of latch circuits LTj (j=1, 2, . . . , n) are respectively connected to buffers BFj (j=1, 2, . . . , n), the output terminals of the buffers BFj are respectively connected to logic circuits LGj (j=1, 2, . . . , n), and the output terminals of the logic circuits LGj are respectively connected to the buffers BFj.
Each logic circuit LGj receives a pulse signal GPS from a pulse signal line and a pulse signal outputted from the corresponding latch circuit LTj through the corresponding buffer BFj, and performs a logical operation using these two signals. Then, each logic circuit LGj outputs the operation result to a corresponding scanning signal line GLj (j=1, 2, . . . , n) as a control signal for determining whether the data signal DAT from the data signal line driving circuit
122
should be sampled or not.
As has been explained, both the data signal line driving circuit
122
and scanning signal line driving circuit
123
use the scanning circuit for sequentially transmitting the pulse signal in sync with the clock signal. A shift register circuit, a decoder circuit and the like can be used as the scanning circuit. However, the shift register circuit is generally used because it has fewer input terminals and a smaller circuit size (fewer transistors).
The shift register circuit is composed of, for example, two clocked inverters and one inverter. The two clocked inverters receive an antiphase clock signal.
Incidentally, in the scanning circuit used in each driving circuit, only one pulse signal is scanned normally, and the power consumption for transmitting the pulse signal is small.
However, in case of an image display apparatus whose scanning circuit is composed of a shift register circuit having a great number of stages, for example, in case of an image display apparatus using a VGA (Video Graphics Array) panel, the data signal line driving circuit and scanning signal line driving circuit demand a 640-stage shift register circuit and a 480-stage shift register circuit, respectively. Further, in case of an image display apparatus using an XGA (Extended Video Graphics Array) panel, the data signal line driving circuit and scanning signal line driving circuit demand a 1024-stage shift register circuit and a 768-stage register circuit, respectively.
Thus, when the scanning circuit is used for the driving circuit that drives the VGA panel or XGA panel, a sum of an input capacitance from a clock signal line of each clocked inverter in the shift register circuit becomes so large that it accounts for most of the consumed power.
Particularly, when the scanning circuit is composed of the polycrystalline silicon thin film transistor as previously mentioned, the performance (carrier mobility, threshold voltage, element voltage withstand, etc.) of the transistor is inferior to the performance of the transistor formed on a monocrystal silicon substrate, provided that both are of the same size. Thus, to improve the performance of the polycrystalline silicon thin film transistor to the same level as the performance of the transistor formed on the monocrystal silicon substrate, the element size (channel length and channel width) must be increased than the transistors on the monocrystal silicon substrate, and a high driving voltage must be supplied. Therefore, the power consumed on the clock signal line increases remarkably.
To solve the above problem, an example liquid crystal display device adopting the dot sequential driving method as shown in
FIG. 17
is disclosed in, for example, Japanese Examined Patent Publication No. 50717/1988 (Tokukoushou No. 63-50717). To be more specific, the shift register circuit in the data signal line driving circuit is divided into a plurality of blocks, and the blocks are sequentially selected at regular time intervals, one at each interval, so that a clock signal CLK is supplied to the latch circuits in the selected block alone.
The above arrangement seems effective to reduce power consumption on the clock signal line if an adequate measure is taken to transmit the pulse signal among the blocks normally. Because the clock signal is selectively transmitted only to the block including latch circuits near the latch circuit to which the pulse signal is transmitted, the number of
Kubota Yasushi
Sakai Tamotsu
Shiraki Ichiro
Conlin David G.
Daley, Jr. William J.
Edwards & Angell LLP
Kovalick Vincent E.
Shalwala Bipin
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