Data separator with compensation circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307208, 328 63, 328155, H03K 117, H03K 513

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active

039506584

ABSTRACT:
A compensation circuit for providing output clock pulses which are accurately spaced timewise with respect to data times at which raw data pulses normally exist on a raw data line assuming no time shifting due to transmission difficulties and including a voltage controlled oscillator and a charge pump circuit for providing a changing voltage applied to the oscillator, and means for providing down and up change frequency signals applied to the charge pump circuit, the up change frequency signal being initiated at the leading edge of a raw data pulse on the raw data line when the raw data pulse is in normal position or is early or late and the down change frequency signal being initiated when the up change frequency signal terminates and terminating midway between data times.

REFERENCES:
patent: 3080487 (1963-03-01), Mellott et al.
patent: 3238462 (1966-03-01), Ballard et al.
patent: 3333205 (1967-07-01), Featherston
patent: 3506923 (1970-04-01), Ambrico et al.
patent: 3510786 (1970-05-01), Paulson
patent: 3731208 (1973-05-01), Laatt et al.
"Phase Detector for Self-Clocking Variable-Frequency Oscillators" by Johnson, IBM Tech. Discl. Bull., Vol. 14, No. 7, Dec. 1971, p. 2171.
"Clock-Phase Correction for Digital Data Recording" by Ho et al., IBM Tech. Discl. Bull., Vol. 17, No. 1, June 1974, pp. 206-207.

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