Data separation and decoding device

Details Data separation and decoding device Data separation and decoding device

2006-05-02

2006-05-02

Le, Vu (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240280

Reexamination Certificate

active

07039114

ABSTRACT:
A clock recovery circuit is provided with an STC counter, an adder for setting the initial value of the STC counter by adding the value of a PCR and the multiplexing delay time; a subtracter for subtracting the multiplexing delay time from the output of the STC counter; a latched STC register for latching the subtraction result of the subtracter; a PCR register for latching the value of the PCR; and a PWM for controlling the frequency of an external clock oscillation source that supplies a clock signal to the STC counter. The clock oscillation source is provided with an LPF and a VCO, wherein a clock signal outputted from the VCO is supplied to the STC counter and a timer within a stream multiplexing circuit. The clock signal outputted from the clock oscillation source is a reference clock signal of an MPEG system. Thereby, the scale of the entire device can be reduced by reducing the number of separation and decoding circuits.

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