Data sensing method used in a memory cell circuit

Details Data sensing method used in a memory cell circuit Data sensing method used in a memory cell circuit

2003-03-14

2004-07-27

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185330

Reexamination Certificate

active

06768678

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention provides a data sensing method used in a memory cell circuit, and more specifically, a method to charge or discharge a loading node using a difference of a first and a second currents to sense a loading voltage.
2. Description of the Prior Art
A memory is a vital component In electronic products. Memory comprises a memory cell array comprising memory cells wherein each memory cell is applied to store a bit of digital data and to perform programming, erasing, and reading of the memory cell according to a variety of control signals transmitted from a word line, a bit line, and et al. A sense amplifier is usually provided in the memory for sensing digital data stored in the memory cell and generating an output signal corresponding to the digital data when the memory is reading the memory cell.
Please refer to FIG.
1
. Illustrated in
FIG. 1
is a schematic diagram of a prior art sense amplifier
10
. As shown
FIG. 1
, the sense amplifier
10
comprises two NMOS transistors
12
and
14
and two PMOS transistors
15
and
18
for providing the necessary amplification to the sense amplifier
10
and an NMOS transistor
20
whose gate is electrically connected to a biasing voltage V
B
for providing a biasing voltage current to the sense amplifier
10
. As mentioned above, the sense amplifier
10
is a differential amplifier amplifying a difference of signals transmitted from two receiving points Vin
+
and Vin
−
of the gates of the NMOS transistors
12
and
14
. The amplified result can be represented by an output signal Vout from an output terminal of the drain of the NMOS transistor
14
.
Usually when the sense amplifier
10
is applied in the memory, the data input point Vin
−
is electrically connected to a memory cell and the reference input point Vin
−
is electrically connected to a reference voltage. The principles of operation of the sense amplifier
10
are as follows. If the memory wants to perform reading on the memory cell, it will control the memory cell with a variety of control signals so that the memory cell will generate a current corresponding to the stored data. Through a specific circuit design, the current will be converted into a voltage being transmitted to the data input point Vin
+
of the sense amplifier
10
. The sense amplifier
10
will apply differential amplification on the voltage received from the data input point Vin
+
and the reference input point Vin
−
for generating an output signal from the outputting terminal Vout corresponding to the data stored in the memory cell.
However, when performing reading, three far more complicated processes, pre-charging, data sensing, and data latching are also applied in the sense amplifier
10
. Before the sense amplifier
10
amplifies data stored in the memory cell, the pre-charging process will be applied to charge voltages of the input points Vin
+
and Vin
−
to the same potential such that the potential value of the data input point Vin
+
is the same as the reference voltage to avoid any difference of the voltages at the input points Vin
+
and Vin
−
generated by a reading process previously performed. The data sensing process represents the above-mentioned process that the sense amplifier
10
is applied to sense data stored in the memory cell and generate a corresponding output signal. After the sense amplifier
10
generates the output signal, a data latching process is applied to keep the output signal in a latch from being lost so that a following circuit can use the output signal.
The pre-charging, data sensing, and data latching processes require a precise sequential control to maintain correctness of the output signal. Thus, a control circuit is usually provided in the memory for generating control signals in proper sequential order. The control circuit is mainly comprised of logic gates and delay circuits. Because a delay circuit requires a large number of capacitors, the control circuit is an integrated circuit occupying a lot of area. To a high density memory having amounts of memory cells wherein the memory cell arrays in the high density memory occupy a huge amount of area, it is reasonable that the control circuit occupies much area. However, for a low density memory having only limited numbers of memory cells, the control circuit occupies just as much area. It is not reasonable for a control circuit for a low density memory to occupy as much area as a control circuit for a high density memory.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a data sensing method used in a memory cell circuit without the need to perform a precise sequential control to overcome the problems of the prior art.
According to the claimed invention, a data sensing method is used in a memory cell circuit. The memory cell circuit includes a first memory cell for storing a non-volatile first data, a second memory cell for storing a non-volatile second data, a first program switchelectrically connected to the first memory cell for controlling the reception of the first data, a second program switchelectrically connected to the second memory cell for controlling the transmission of the second data, and a biasing circuit. The biasing circuit has a first switch, a second switch, and a loading node wherein the first switch is electrically connected between the first memory cell and the loading node and the second switch is electrically connected between the second memory cell and the loading node.
The method comprises turning on the first and the second program switches and turning off the first and the second switches to make the memory cells stay in a program mode in order to write the first data to the first memory cell and to write the second data to the second memory cell, turning off the first and the second program switches and turning on the first and the second switches to make the memory cell circuit stay in a read mode in order to transmit a first current corresponding to the first data from the first memory cell to the biasing circuit and to transmit a second current corresponding to the second data from the biasing circuit to the second memory cell, and charging or discharging the loading node using a difference of the first and the second currents to sense a loading voltage.
The claimed invention applies currents generated by the memory cell to charge or discharge the loading node to sense the loading voltage and read data stored in the memory cell. Complicated processes such as pre-charging, data sensing, and data latching are not applied in the present invention. Thus, a control circuit occupying a huge area is no longer required.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5859798 (1999-01-01), Yero
patent: 5917753 (1999-06-01), Dallabora et al.
patent: 6191979 (2001-02-01), Uekubo
patent: 6259645 (2001-07-01), Chen et al.
patent: 6625062 (2003-09-01), Won et al.
patent: 6687162 (2004-02-01), Hsueh et al.

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