Data sense apparatus for use in multi-threshold read only memory

Details Data sense apparatus for use in multi-threshold read only memory Data sense apparatus for use in multi-threshold read only memory

1981-01-28

1983-09-13

Stellar, George G.

Static information storage and retrieval

Read only systems

Semiconductive

365168, G11C 700, G11C 1156, G11C 1700

Patent

active

044046553

ABSTRACT:
A read only memory in which the memory cells are single metal gate or silicon gate field effect transistors. Each FET has one of several different thresholds or states. The size or area of the FET gates at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instant. The output of a cell is fed to several flip-flops, which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128K on a single chip. In another embodiment the input to the gates is a step, and the cells are all rendered conducting simultaneously. The amount of current drawn by each gate however, depends upon the doping in the gate region. The amplitude of the current being drawn by a selected cell is compared with the reference , this in turn is decoded to indicate the state of that cell.

REFERENCES:
patent: 4192014 (1980-03-01), Craycraft
patent: 4202044 (1980-05-01), Beilstein, Jr. et al.
patent: 4272830 (1981-06-01), Moench
patent: 4287570 (1981-09-01), Stark
IEEE Transactions on Electron Devices, vol. ED-21, No. 6, Jun. 1974, pp. 324-331, "Ion Implantation for Threshold Control in Cosmos Circuits," E. C. Douglas et al. Copy in ACI 254.

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