Data selection circuit

Details Data selection circuit Data selection circuit

1994-09-13

1996-04-16

Weldon, Ulysses

Computer graphics processing and selective visual display system

Plural physical display element control system

Segmented display elements

345 50, 345 52, G09G 318

Patent

active

055087159

ABSTRACT:
The data selection circuit of 1
Duty-1/m Bias activating scheme of the present invention includes (m+1) selectors which are independently provided. Each selector includes 2.sup.n decoder sections for subjecting n-bit select data supplied from the exterior to different decoding processes, and 2.sup.n inverter sections respectively connected in series with the decoder sections, outputs of the inverter sections being connected in a wired OR connection configuration. The 2.sup.n .times.(m+1) inverter sections are supplied with different preset input signals determined by integers m, n (m.gtoreq.2, n.gtoreq.2) and the logic of the corresponding decoding sections from the exterior. Thus, the data selection circuit of 1
Duty-1/m Bias scheme in which the number of necessary transistors is significantly reduced can be provided.

REFERENCES:
patent: 4060802 (1977-11-01), Matsuki
patent: 4781437 (1988-11-01), Shields et al.
patent: 4822142 (1989-04-01), Yasui
patent: 4855724 (1989-08-01), Yang
patent: 4931787 (1990-06-01), Shannon
patent: 5151689 (1992-09-01), Kabuto et al.
High Speed CMOS 74HC/HCT/HCU Logic Family. Data Handbook Integrated Circuits, Book IC06, "Philips Semiconductors", 1991, pp. 531-535.
IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984, W. R. Griffin, et al., "CMOS Select 1 Of N Multiplexer", pp. 651-652.

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