Data retiming circuit

Details Data retiming circuit Data retiming circuit

1997-05-20

1999-03-23

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

327144, 375359, H04L 700

Patent

active

058865527

ABSTRACT:
An improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop. The circuit includes a first delay unit for increasing a rising and falling time from an externally inputted data by a predetermined time as much as a clock phase difference, a first data latch unit connected so that the phase from the clock generator can be to correspond with the number of different clocks for latching the data inputted in accordance with the clock, a second delay unit for receiving the data from the first delay unit and for delaying the data so that a clock is selected and coincides with the timing until the output of the clock, a data latch state determination unit for determining the logic signal state of the data latched by the first data latch unit in an analog method, a clock selection unit for logically compares a plurality of clocks inputted and a data state signal outputted from the data latch state determination unit and for selecting a retiming signal, and a second data latch unit for latching the data relayed by the second delay unit in accordance with the retiming clock signal.

REFERENCES:
patent: 4841551 (1989-06-01), Avaneas
patent: 5452324 (1995-09-01), Lewis et al.
patent: 5671258 (1997-09-01), Burns et al.
ILEE Journal of Solid-State Circuits, vol. 24, No. 1 Feb., 1989, Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test by Jens U. Horstmann, Hans W. Eichel and Robert L. Coates pp. 146-157.

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