Data retention circuit

Details Data retention circuit Data retention circuit

1993-07-23

1995-06-27

Canney, Vincent P.

Excavating

371 22, 371 571, G06F 1100

Patent

active

054287677

ABSTRACT:
A data retention circuit prevents erroneous data from being written into a backup RAM, even when a software upset occurs so that a secure data retention can be obtained in a backup RAM of a game machine. A backup chip select signal output from an address decoder, outputs of an enable circuit, and a software upset detection circuit are used to enable a backup memory write process. The enable circuit outputs an enable signal only when a predetermined ID code signal sequence is supplied from a CPU. When inconsistency between an access pattern, a read, and a write signal occurs, the software upset detection circuit outputs a software upset detection signal. An AND gate blocks a supply of the backup chip select signal to the backup memory according to a combination of the software upset detection signal and the enable signal.

REFERENCES:
patent: 4926427 (1990-05-01), Remein
patent: 5130946 (1992-07-01), Watanabe
The Design of OS/2 by H. M. Deitel et al., .COPYRGT.1992 by Addison-Weasley Publishing Co. pp. 6 and 7.
Operating System Concepts, Third Edition by A. Silberschatz et al., .COPYRGT.1991 by Addison-Weasley Publishing Co. pp. 397-409.

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