Data retaining circuit

Details Data retaining circuit Data retaining circuit

2005-07-26

2005-07-26

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000, C327S218000

Reexamination Certificate

active

06922094

ABSTRACT:
A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.

REFERENCES:
patent: 5111429 (1992-05-01), Whitaker
patent: 5525923 (1996-06-01), Bialas, Jr. et al.
patent: 6026011 (2000-02-01), Zhang
patent: 6259643 (2001-07-01), Li
patent: 6275080 (2001-08-01), Phan et al.
patent: 6327176 (2001-12-01), Li et al.
French Patent Office search report dated Nov. 9, 2004 for corresponding French patent Application 0214516.
K. J. Hass, et al., “Mitigating Single Event Upsets From Combinational Logic,” 7thNASA Symposium on VLSI Design 1998, pp. 4.1.1-4.1.10.

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