Data resynchronization circuit

Details Data resynchronization circuit Data resynchronization circuit

2005-01-04

2005-01-04

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C375S376000, C327S156000

Reexamination Certificate

active

06838945

ABSTRACT:
An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.

REFERENCES:
patent: 5537068 (1996-07-01), Konno
patent: 5619148 (1997-04-01), Guo
patent: 5621774 (1997-04-01), Ishibashi et al.
patent: 5625649 (1997-04-01), Ishizu
patent: 5689533 (1997-11-01), Brauns et al.
patent: 5948083 (1999-09-01), Gervasi
Yang et al (“A 0.8-um CMOS 2.5 Gb/s Oversampling Receiver and Transmiter for Serial Links”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp 2015-2023).

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