Data resynchronization circuit

Details Data resynchronization circuit Data resynchronization circuit

1999-12-31

2003-10-28

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

C375S375000, C375S372000, C327S158000, C710S061000, C713S401000

Reexamination Certificate

active

06639956

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to delay locked loop based circuits and in particular to delay locked loop based circuits for use with an IEEE 1394-1995 decoder, IEEE Std 1394-1995, published Aug. 30, 1996.
BACKGROUND
IEEE 1394-1995 decoders are based on a non return to zero (NRZ) transmission of data signal in which a strobe is also transmitted to recover the digital data from the NRZ data signal. From the NRZ data signal and the strobe, a recovery clock may be constructed which is used to extract the actual digital data from the NRZ data signal. The transmission of NRZ data signal and the strobe allows for a reliable transmission and receipt of digital data. During packet transmission, there is only a single node transmitting on the bus, so the entire media can operate in a half duplex mode using the two signals: Data and Strobe. As shown in
FIG. 1
, NRZ data is transmitted on Data and is accompanied by the Strobe signal which changes state whenever two consecutive NRZ data bits are the same, ensuring that a transition occurs on either Data or Strobe for each data bit.
FIG. 2
illustrates an example of an IEEE 1394-1995 decoder
5
. Decoder
5
receives the NRZ data signal and the strobe to generate a recovery clock using a plurality of flip flops
10
,
15
, and
20
to generate data data_
1
, data data_
0
and a quarter clock qrt_clk, respectively. The three signals are then used to construct the original digital data transmitted by the source. A clock that transitions each bit period can be derived from the exclusive-or of Data with Strobe. The primary rationale for use of this transmission code is to improve the skew tolerance of information to be transferred across the serial bus.
However, the generated signals from the decoder are not useful because the recovered data and the recovered clock need to be in sync with the local clock of the circuit using the data. Generally, this function is performed by a data re-timing circuit. Previously, a phase locked loop (PLL) circuit was used for timing and carrier recovery to ensure optimal data sampling using a local clock. However, there are many disadvantages to using a PLL based circuit, in particular, in high speed and low power applications. For example, PLL based circuits require a long acquisition time, normally in the range of 100-2000 cycles before a “lock” takes place. In high speed circuits, such delay is not acceptable. To minimize the acquisition time, one previous method maintained a certain level of transition activity as to maintain a PLL lock. However, such transition activity generally resulted in power dissipation which in certain instances is undesirable.
Accordingly, there is a need for an IEEE 1394-1995 compatible resync circuit that is suitable for high speed low power applications and that has a relatively short acquisition time.
SUMMARY
In accordance with an embodiment of the invention, there is disclosed an apparatus including three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.


REFERENCES:
patent: 5537068 (1996-07-01), Konno
patent: 5619148 (1997-04-01), Guo
patent: 5621774 (1997-04-01), Ishibashi et al.
patent: 5625649 (1997-04-01), Ishizu
patent: 5689533 (1997-11-01), Brauns et al.
patent: 5948083 (1999-09-01), Gervasi
Yang et al (“A 0.8-um CMOS 2.5 Gb/s Oversampling Receiver and Transmiter for Serial Links”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp 2015-2023).

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