Data resynchronization between modules sharing a common clock

Details Data resynchronization between modules sharing a common clock Data resynchronization between modules sharing a common clock

1999-07-20

2004-06-01

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

C375S372000, C375S354000, C711S155000

Reexamination Certificate

active

06744833

ABSTRACT:

BACKGROUND OF THE INVENTION
The current invention relates to data transfer between modules, and more particularly to a scheme for resynchronizing data between modules sharing a common clock.
The problem presented, as shown in
FIG. 1
, is that of transferring data across a boundary, such as between two separate modules, where the clock frequency is common on both sides of the boundary but the clock delay across the boundary is unknown. Although first-in/first-out (FIFO) buffers are typically used in smoothing data flow across a boundary where the clock rates on opposite sides of the boundary are different, the current problem may be addressed by inserting a FIFO buffer between the two modules, with the data being clocked into the FIFO buffer by the clock on one side of the boundary and the data being clocked out of the FIFO buffer by the clock on the other side of the boundary. However this adds to the expense of the circuitry by requiring an additional component between the two modules.
What is desired is a scheme for resynchronizing data between modules sharing a common clock without using an external FIFO buffer.
BRIEF SUMMARY OF THE INVENTION
Accordingly the present invention provides a scheme for resynchronizing data between modules sharing a common clock. Successive data records from a first module are stored in successive registers that are enabled in a recirculating manner by the common clock. A multiplexer in a second module selects the outputs from the successive registers in a recirculating manner in response to a delayed version of the common clock in such a manner that the register selected is one not just written into or just about to be written into to assure that the data in the selected register is not in a metastable state. In this manner the data is resynchronized in the second module no matter what the time delay is for the common clock.
The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.


REFERENCES:
patent: 3702988 (1972-11-01), Haney et al.
patent: 4596026 (1986-06-01), Cease et al.
patent: 5487092 (1996-01-01), Finney et al.
patent: 6236623 (2001-05-01), Read et al.

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