Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
1998-01-28
2001-02-13
Tran, Thai (Department: 2715)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000, C348S461000, C348S465000
Reexamination Certificate
active
06188829
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a data reproduction apparatus for reproducing character data from a character multiplexing video signal which is demodulated from a received signal of character multiplexing television broadcast, and more particularly to an apparatus for generating a clock signal for character data reproduction based on a character data identification sync signal attached to a character multiplexing video signal and reproducing character data based on the clock signal, and the apparatus is used for a television receiver or video tape player, for example.
The character multiplexing video signal contains character information in the form of character data or font data in the vertical scanning period of the video signal, and in a period prior to the character data, a bit sync signal called a CRI (Clock Run In) signal and a byte sync signal called an FC (framing code) signal are sequentially attached as the character data identification sync signal.
In the specification of the character multiplexing video signal, the CRI signal is 16 pulse signals (pulse signals of 8 cycles) having a pattern of “1010101010101010” and the FC signal is 8 pulse signals having a pattern of “11100100”. The pulse period (frequency) of the CRI signal is determined according to the type of the specification.
Conventionally, in a data reproduction apparatus for character multiplexing video signal, the CRI signal in the character multiplexing video signal is detected to generate a clock signal for character data reproduction and the character data is reproduced based on the clock signal.
However, the CRI signal which conforms with the specification is not always contained in a video signal input of a video signal input terminal
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even at the time of reception of the character multiplexing television broadcast according to the conditions of countries or regions giving the character multiplexing television broadcast and, for example, the period of the CRI signal is short or part of the pulse of the CRI signal is lost in some cases.
In such a case, in the conventional data reproducing apparatus, the CRI signal cannot be stably detected and a clock signal for character data reproduction cannot be stably generated, and as a result, character data cannot be stably reproduced in some cases.
Therefore, for example, when an equipment containing a data reproduction apparatus for character multiplexing video signal for export specification is manufactured, it is necessary to recheck whether a system for generating a clock signal for character data reproduction based on the CRI signal can be used or not.
As described above, the data reproduction apparatus for character multiplexing video signal has a problem that a clock signal for character data reproduction cannot be stably generated in some cases according to the conditions of the countries or regions giving the character multiplexing television broadcast, and therefore, character data cannot be stably reproduced in some cases.
BRIEF SUMMARY OF THE INVENTION
An object of this invention is to provide a data reproduction apparatus for character multiplexing video signal which can stably generate a clock signal for character data reproduction and stably reproduce character data without receiving a substantial influence by the conditions of the countries or regions giving the character multiplexing television broadcast.
This invention provides a data reproduction apparatus for character multiplexing video signal which includes an A/D converter circuit for converting a character multiplexing video signal into a digital video signal; a framing code detecting/clock generating circuit for receiving the digital video signal from the A/D converter circuit and detecting a framing code signal contained in the received signal to generate a clock signal for character data reproduction; a delay circuit for delaying the digital video signal input from the A/D converter circuit by a period of time corresponding to time required for the framing code detecting/clock generating circuit to generate the clock signal; and a data reproducing circuit for reproducing character data by sampling the digital video signal delayed by the delay circuit by use of the clock signal generated from the framing code detecting/clock generating circuit.
This invention provides a data reproduction apparatus for character multiplexing video signal comprising an A/D converter circuit for converting a character multiplexing video signal into a digital video signal; a framing code detecting/clock generating circuit for receiving the digital video signal from the A/D converter circuit and detecting a framing code signal contained in the received signal to generate a clock signal for character data reproduction; a delay circuit for delaying the digital video signal input from the A/D converter circuit by a period of time corresponding to time required for the framing code detecting/clock generating circuit to generate the clock signal; and a data reproducing circuit for reproducing character data by sampling the digital video signal delayed by the delay circuit in synchronism with the clock signal generated from the framing code detecting/clock generating circuit, the framing code detecting/clock generating circuit includes a clock generating circuit for generating plural-phase clock signals of at least three phases each having a frequency twice the bit rate of data contained in the digital video signal; a plurality of framing code detection circuits for detecting framing code signals from the digital video signal and outputting the amplitude levels of the framing signals in synchronism with the respective plural-phase clock signals; a maximum level series determination circuit for determining the magnitude relation between the amplitude levels output from the plurality of framing code detection circuits and outputting different logic levels for one of a plurality of series in which the input has the highest level and the framing code detection frequency is highest and the other series; and a clock selection circuit for receiving outputs of the plurality of framing code detection circuits and outputs of plural series from the maximum level series determination circuit and outputting a clock signal of one of the plural series corresponding to the plural-phase clock signals of the clock generating circuit in which the framing code detection frequency is highest as a data reproduction clock.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4277838 (1981-07-01), Chambers
patent: 6046775 (2000-04-01), Jonnalagadda et al.
patent: 6111612 (2000-08-01), Ozkan et al.
patent: 2 188 816 (1987-10-01), None
Kato Koji
Watanabe Masayuki
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tran Thai
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