Data reproducing method and data reproducing unit

Details Data reproducing method and data reproducing unit Data reproducing method and data reproducing unit

1996-02-23

1998-07-07

Pham, Chi H.

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375376, H04L 700, H03D 324

Patent

active

057780323

ABSTRACT:
A sampler (1) samples an inputted base band signal in accordance with a sampling clock, and holds a sample value (S.sub.n). Delay circuits (7, 8) hold sample values (S.sub.n-1, S.sub.n-2), respectively. A decision circuit (2) determines the sample value (S.sub.n-1), and outputs data (d.sub.n-1). A constant multiplier (16) multiplies the data (d.sub.n -1) by a constant (.alpha.). A subtracter (17) subtracts the data (d.sub.n-1) from the sample value (S.sub.n-1). Another subtracter (13) subtracts the sample value (S.sub.n) from the sample value (S.sub.n-2). A multiplier (14) multiplies the output of the subtracter (17) by that of the subtracter (13), and outputs a timing error signal. A low-pass filter (15) extracts a low frequency component of the timing error signal, and supplies a control voltage to a voltage controlled oscillator (6). The voltage controlled oscillator (6) outputs a sampling clock having a frequency which depends on the control voltage.

REFERENCES:
patent: 5455847 (1995-10-01), Guilford et al.
patent: 5535252 (1996-07-01), Kobayashi
patent: 5638409 (1997-06-01), Awata et al.
patent: 5706314 (1998-01-01), Davis et al.

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