Data reduction circuit with a differential pulse code modulator

Details Data reduction circuit with a differential pulse code modulator Data reduction circuit with a differential pulse code modulator

1987-04-13

1988-05-31

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

375 27, 375 30, H04N 712

Patent

active

047485035

ABSTRACT:
A data reduction circuit employs a differential pulse code modulator for input video signals where the time-critical loop includes a loop subtractor (s2), a quantizer (q), and a loop delay element (v3), so that differential pulse code modulation can be performed at higher clock rates than with conventional architectures. With 2 .mu.m CMOS or N-channel MOS technology, for example, clock rates of 17 to 20 MHz are possible. The circuit includes a limiter circuit which applies the input video signals to the loop subtractor minuend input after processing the same. The output of the delay element in the loop is applied to inputs of a first adder, a vertical predictor and a constant multiplier, the multiplier receive a weighting factor equal to the square of a given weighting factor with the output of the multiplier applied to the subtrahend input of a first subtractor whose output is coupled to the input of the loop subtractor via a delay element. The output of the vertical predictor is applied respectively to the inputs of another constant multiplier, another delay element and to the subtrahend input of another subtractor. The outputs of these units are applied to enable input video signals as processed to be applied to the minuend input of the first subtractor to thereby reduce the circuitry needed in the time critical loop.

REFERENCES:
patent: 4255763 (1981-03-01), Maxemchuk et al.
patent: 4375013 (1983-02-01), Cointot et al.
patent: 4460923 (1984-07-01), Hirano et al.
patent: 4541102 (1985-09-01), Grallert
patent: 4562468 (1985-12-01), Koga
patent: 4706260 (1987-11-01), Fedele et al.

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