Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking
Reexamination Certificate
1998-12-08
2001-06-19
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Data clocking
C360S065000
Reexamination Certificate
active
06249395
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data recovery systems and more particularly to systems utilizing partial response maximum-likelihood (PRML) detection.
Data recovery systems are used in a variety of applications. In one application, such system is used to recover (i.e., read) data stored on a magnetic disk of the type used as hard drives in computer data storage systems. In one type of such data storage system, a predetermined preamble pattern is written onto the magnetic disk before the start of any block of data to be stored. The preamble pattern is used during the read operation to acquire initial gain, frequency and phase lock to the data read from the disk. Thus, when data is read from the disk, the preamble is used by the read channel during a preamble recovery mode to obtain clock (i.e., sampling or timing) pulses for a subsequent data recovery mode.
The data read from the magnetic disk is typically passed through an analog equalization filter prior to passing to succeeding stages of the data recovery system. The analog equalization filter is configured to shape the sequence of preamble pulses and data pulses into pulses having a predetermined waveform characteristic. The analog equalization filter has non-linear change in phase as a function of frequency characteristic. The analog equalization filter produces pulses that are fed to an analog-to-digital converter . The analog to digital converter converts samples of the shaped pulses into corresponding digital words in response to the clock pulses (i.e., sampling pulses) fed to a clock input of the converter. In one arrangement, such as in U.S. Pat. No. 5,220,466, a pair of feedback loops is coupled between an output of the analog to digital converter and the clock pulse input to such converter. A first one of the feedback loops is used during the data recovery mode and includes a digital filter fed by the digital filter words produced by the analog to digital converter. The digital filter has coefficients selected to compensate for the non-linear change in the magnitude and phase as a function of frequency characteristic of the equalization filter. A tracking gain and phase control section is fed by the digital filter and is responsive to the digital words representative of the data pulses for producing the clock pulses for the analog to digital converter during the data recovery mode.
However, in order to rapidly synchronize the clock pulse frequency and phase to the preamble pulse frequency f
p
and phase during the preamble acquisition mode, the digital filter is by-passed (i.e., the first feedback loop is disabled) and a second one of the pair of feedback loops is used. That is, the second feedback loop is used during the preamble acquisition phase to lock onto the frequency and phase of the preamble for subsequent switch-over to the first feedback loop. The second feedback loop includes an acquisition gain and timing control section responsive to the digital words representative of the preamble pulses for producing clock pulses for the converter which are synchronized (i.e., locked) in frequency and phase to the preamble pulses.
The use of an asymmetric digital filter can improve data recovery performance. That is, because the analog equalization filter may have a non-linear phase vs. frequency characteristic, an asymmetric digital filter may provide better compensation. However, when switching from the preamble acquisition mode to the data recovery mode, an undesirable a phase step change may occur in the system.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data recovery system is provided. The data is represented by a sequence of preamble pulses having a predetermined sequence followed by data pulses. An analog to digital converter is provided to convert samples of the preamble pulses and the data pulses into corresponding digital words in response to clock pulses fed to a clock input of the converter. A selected one of a pair of feedback loops is coupled to an output of the analog to digital converter to produce the clock pulses for the converter; a first one during a data recovery mode and a second one during a preceding preamble acquisition mode. The first one of the feedback loops includes an asymmetric digital filter fed by the digital words produced by the analog to digital filter. The first one of the feedback loops produces the clock pulses during a data recovery mode in accordance with a first phase error signal. The first phase error signal is related to a phase difference between the clock pulses to the converter and data pulses produced by the asymmetric digital filter. The first feedback loop adjusts the phase of the clock pulses to the converter in accordance with the first phase error signal to produce a predetermined phase difference between the converted data pulses and the clock pulses. The second feedback loop by-passes the asymmetric digital filter during a preceding preamble acquisition mode and produces the clock pulses to the converter during the preamble acquisition mode. The second feedback loop produces a second phase error signal related to a phase difference between the clock pulses to the converter and converted preamble pulses produced by the analog to digital converter and a predetermined phase difference, or offset phase, between the converted preamble pulses and the clock pulses. The offset is related to a phase shift produced by the asymmetric digital filter.
With such an arrangement, because the first and second phase error signals produced by the pair of feedback loops are substantially equal, a seamless switching from the preamble acquisition mode to the data recovery mode is accomplished.
In accordance with another feature of the invention, a data recovery system is provided wherein the data recovered from such system is represented by a sequence of data pulses. The system includes an analog equalization filter fed by a predetermined sequence of preamble pulses during a preamble acquisition mode followed by the sequence of the data pulses during a subsequent data recovery mode. The analog equalization filter is configured to shape the sequence of preamble pulses and data pulses into pulses having a predetermined waveform characteristic. The analog equalization filter may have a non-linear change in phase as a function of frequency characteristic. The data recovery system includes an analog to digital converter fed by the analog equalization filter for converting samples of the shaped pulses fed thereto into corresponding digital words in response to clock pulses fed to a clock input of the converter. The system also includes a pair of feedback loops. A first one of the loops is coupled between an output of the analog to digital converter and the clock pulse input to such converter through an asymmetric digital filter during a data recovery mode and a second one of the loops is coupled between the output of the analog to digital converter and the clock pulse input to such converter with the asymmetric digital filter by-passed, during a preceding preamble recovery mode. The asymmetric digital filter has coefficients selected to compensate for the non-linear change in phase as a function of frequency characteristic of the equalization filter. The first feedback loop includes a data phase error calculator section fed by the asymmetric digital filter. The data phase error calculator section is responsive to the digital words fed thereto by the asymmetric digital filter and produces a data recovery mode phase error control signal. The second one of the feedback loops includes a preamble phase error calculator section responsive to the digital words produced by the analog to digital converter and representative of the preamble pulses and an offset phase shift, determined in accordance with the coefficients of the asymmetric digital filter, for producing a preamble acquisition mode phase error control signal. The preamble acquisition mode phase error control signal is used to control the frequency and phase of the clock pulses
Faber Alan T.
Galanthay Theodore E.
Jorgenson Lisa K.
Morris James H.
STMicroelectronics N.V.
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