Data recovery system for use with a high speed serial link betwe

Pulse or digital communications – Repeaters – Testing

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360 43, 375 52, 375 88, 375 95, H04L 2710

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active

042875960

ABSTRACT:
A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal. The control signal is also used to generate a recovered data signal by clocking the control signal into two cascaded flip-flops and logically combining the outputs of the two cascaded flip-flops.

REFERENCES:
patent: 3377560 (1968-04-01), Renshaw
patent: 3437932 (1969-04-01), Malakoff

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