Data recovery phase locked loop

Details Data recovery phase locked loop Data recovery phase locked loop

1996-06-05

1998-04-28

Callahan, Timothy P.

Oscillators

With frequency calibration or testing

331 14, 331 17, 327156, H03L 7085, H03L 7093

Patent

active

057450110

ABSTRACT:
A clock recovery phase locked loop system is described. One embodiment has a voltage controlled oscillator divider (the signal of which is compared with a REFCLK divider signal), a voltage stimulus input where a test voltage is applied, a time stimulus input where a digital input with appropriate pulse width is applied and a monitor (output) where the results of the measurement can be observed. A test system is included which applies a series of analog voltages to the voltage stimulus input. For each analog voltage, the test system apply a series of pulses to the time stimulus input. By monitoring (a) the level on the monitor output and (b) the time at which it switches, the VCO gain can be calculated. This allows a direct measurement of VCO gain (K.sub.v) using conventional automatic test equipment used to test digital logic or memory devices.

REFERENCES:
patent: 4943788 (1990-07-01), Laws et al.
patent: 5015970 (1991-05-01), Williams et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5525935 (1996-06-01), Joo et al.

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