Data recovery circuit with large retime margin

Details Data recovery circuit with large retime margin Data recovery circuit with large retime margin

1995-08-28

1997-11-18

Bocure, Tesfaldet

Pulse or digital communications

Multilevel

341 68, 375359, H04L 2534, H04L 2549

Patent

active

056895305

ABSTRACT:
A circuit for recovering a clock signal from incoming data and for retiming the incoming data comprises circuitry for generating a plurality of phased clock signals responsive to a selected frequency and clock recovery circuitry for generating a recovered clock from the plurality of phased clocks and the incoming data. The recovered clock is used to retime the data, which may be either RZ or NRZ data. To recover clock from the incoming data, the presence of a logic "1" is detected in one or more data streams and the phase of the data relative to the phased clocks is determined. Hold circuitry stores the phase information during the interval between logic "1" bits and aligns the phase information with the leading phased clock. Compare circuitry and counter circuitry detect changes in phase information to insure that a change is not merely the result of a metastable anomaly. Phase control circuitry uses phase information from the compare block to switch between phased clocks to generate the glitchless recovered clock. The recovered clock is used by the data retime circuitry to retime the data with the recovered clock. A multi-tap delay line can be used to generate a plurality of phased clock signals from a selected data frequency, with the clock recovery circuitry using a predetermined number of the plurality of phased clocks to generate the recovered clock responsive to the frequency of the incoming data.

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