Patent
1988-07-18
1992-06-09
Shaw, Gareth D.
395275, DIG 1, DIG 1, DIG 1, DIG 1, DIG 1, DIG 1, DIG 1, G06F 1312
Patent
active
051214806
ABSTRACT:
A circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers. Parallel transition memories in conjunction with a buffer memory under common control of a buffer manager increase the transfer efficiency between the data storage unit and the host computer. Selectable register banks provide interface compatibility with multiple host computers for implementation of the invention.
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Acost Marc
Bonke Carl
Jen Han
Loomis John C.
Shaw Gareth D.
Western Digital Corporation
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