Data receiver technology

Details Data receiver technology Data receiver technology

2001-04-25

2003-03-18

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S563000

Reexamination Certificate

active

06535032

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to data receiver circuits.
BACKGROUND OF THE INVENTION
Data receiver circuitry is used to sample data signals communicated between electronic devices. Numerous data receiver techniques and circuits have been implemented to increase accuracy and data acquisition speed. One type of data receiver circuit samples incoming data on an active transition of a clock signal. Another type of receiver circuit samples the incoming data signal on both active and inactive transitions of the clock signal.
Referring to
FIGS. 1 and 2
, a prior art receiver circuit uses a pair of timing reference clocks in a point-to-point data communication system. The clock signals are complements of each other (CLK and /CLK). The receiver circuit uses two comparators (Comparator A and Comparator B) to compare the data signal with CLK and /CLK, respectively. Each comparator is a differential amplifier followed by a NAND gate. A receiver-enable signal drives a second input of the NAND gate. The outputs of both the comparators are connected to the receiver output through steering logic (consisting of two multiplexers with only one of the multiplexers being enabled at any given time). The steering logic determines which comparator should be connected to the output as shown in FIG.
2
.
As depicted in
FIG. 1
, there are eight combinations of data input CLK and /CLK in the two consecutive bit times. In cases
1
and
6
the data input makes a differential comparison with CLK using Comparator A, in cases
2
and
5
the data input makes a differential comparison with /CLK using Comparator B, in the other four cases the data does not change. In case
1
, the data and CLK both change, thus Comparator A still has full differential signal at the end of the first bit time. The steering logic is essentially an exclusive OR function between data and CLK. If both of them change, the same comparator remains connected to the data output through the enabled multiplexer for the next bit time. If the data does not change, the steering logic will disconnect the data output from the previous comparator and connect the other comparator to the data output. The steering logic essentially passes the output of Comparator A to the data output and keeps the enabled multiplexer connected to the output for the next bit time. The operation is similar for case
6
relative to Comparator A and CLK and to cases
2
and
5
using Comparator B and /CLK, since all these cases have a data input change relative to the previous bit time. When the data input does not change (as in case
3
), the steering logic first disables the enabled multiplexer before the differential signal between the data input and CLK disappears on Comparator A and then enables the multiplexer connecting Comparator B to the data output. Since CLK and /CLK are complementary, by the end of the first bit time Comparator B has full differential signal, is driving the data output to the existing state, and is ready for the second bit time. The same CLKs can be used for multiple data inputs.
In case
1
(
FIG. 1
) data input goes from high to low and CLK goes from low to high, each of them swinging about 0.5 V. When they cross each other, the comparator (a differential amplifier followed by a NAND gate) detects the differential voltage very quickly. So in this case, the comparator started with a full differential signal of about 0.5 V with data input being higher than CLK and ended the bit time with the same difference, but CLK being higher than the data input. If the data input does NOT change, as shown in case
3
(FIG.
1
), the CLK and data input become equal at a later time than they do in their crossing in case
1
and when the output of the Comparator A becomes a weak high or indeterminate in case
3
.
FIG. 3
is a schematic diagram of the prior art receiver
100
of FIG.
2
. Circuit
100
includes a receiver
102
to compare a Data signal
114
with a Clock signal
116
. Receiver
102
provides an output
106
to multiplex circuit
120
. Circuit
100
also includes a receiver
104
to compare Data signal
114
with a /Clock signal
116
(complementary Clock). Receiver
104
provides an output
108
to multiplex circuit
120
. Multiplex circuit
120
routes a signal from either output connection
106
or
108
to multiplex output
122
. The multiplex circuit is controlled in response to XNOR-A circuit
124
and XNOR-B circuit
126
, as explained below. Output signals from the multiplex circuit are routed through output circuit
128
to an output connection
140
. A clock receiver circuit
110
provides internal Clock
121
and/Clock
113
signals.
Table 1 and Table 2 illustrate the operation of XNOR-A circuit
124
and XNOR-B circuit
126
, respectively. The B input has the same logic state as output
122
of the multiplex circuit
120
, and the A input is its complement. XNOR-A
124
provides an output signal (OUT-A) on node
132
. Likewise, XNOR-B
126
provides an output signal (OUT-B) on node
134
. In operation, the data signal from node
106
is selected by multiplex circuit
120
when the signal on node
132
is low. Similarly, the data signal from node
108
is selected by multiplex circuit
120
when the signal on node
134
is low. Signals on nodes
132
and
134
are not low at the same time, see Tables 1 and 2. An enable signal is provided on connection
112
to enable receiver circuits
102
,
104
and
110
. The multiplex circuit
120
is also coupled to the enable signal.
TABLE 1
A
B
CLK
OUT-A
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
TABLE 2
A
B
/CLK
OUT-B
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
The data receiver circuitry of
FIG. 1
is complex and fails to provide repeatable data acquisition timing. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a simplified data receiver circuit.
SUMMARY OF THE INVENTION
The above-mentioned problems with data receiver circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a data receiver circuit comprises a first differential circuit comparing a first clock signal to a data signal, a second differential circuit comparing a second clock signal to the data signal, and a current mirror circuit coupled to the first and second comparator circuits. The first and second comparator circuits control an output of the current mirror circuit.
In another embodiment, a data receiver circuit includes a current mirror circuit comprising a first diode connected p-channel transistor having a gate coupled to its drain, a source of the first p-channel transistor is coupled to a voltage supply, and a second p-channel transistor having a gate coupled to the gate of the first p-channel transistor. A source of the second p-channel transistor is coupled to the voltage supply. The data receiver further includes a first differential circuit comprising a first n-channel transistor coupled between the drain of the first p-channel transistor and a first pull-down transistor. A gate of the first n-channel transistor is coupled to receive a first clock signal. The first differential circuit further comprises a second n-channel transistor coupled between a drain of the second p-channel transistor and the first pull-down transistor. A gate of the second n-channel transistor is coupled to receive a data signal. The data receiver further includes a second differential circuit comprising a third n-channel transistor coupled between the drain of the first p-channel transistor and a second pull-down transistor. A gate of the third n-channel transistor is coupled to receive a second clock signal. The second differential circuit further comprises a fourth n-channel transistor coupled between the drain of the second p-channel transistor and the second pull-down transistor. A gate of the fourth n-channel transistor is coupled to receive the da

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