Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-10-18
2004-11-16
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S336000
Reexamination Certificate
active
06819146
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a data receiver and a data receiving method that integrate received differential reference signals and data synchronized with a clock signal and detect the received data.
2. Description of the Related Art
Differential receiving and/or transmitting data is one method for receiving and transmitting data between semiconductor devices. However, the method is disadvantageous in that the number of data lines needed to receive/transmit data is large.
FIG. 1
is a block diagram of a data receiver that uses conventional single reference signaling.
FIG. 2
is a timing diagram showing the levels of the signals of FIG.
1
.
With reference to
FIGS. 1 and 2
, a data receiver
10
has one reference signal line
1
used to receive a reference signal VREF, and N data lines
3
,
5
, . . . ,
7
used to receive N data DATA
1
, DATA
2
, . . . , and DATAN. The data receiver
10
compares the reference signal VREF with each of the N data lines DATA
1
, DATA
2
, . . . , DATAN and detects the received data.
However, since the data receiver
10
that uses the single reference signaling technique is sensitive to noise, it cannot receive data at a high speed. In addition, due to attenuation of a transmission line, the faster the data transmission speed, the smaller the data size. As a result, the voltage difference DD1 between the reference signal VREF and the data DATA
1
, DATA
2
, . . . , DATAN is reduced. Therefore, it is difficult to detect the received data accurately.
FIG. 3
is a block diagram of another data receiver
20
that uses conventional differential signaling.
FIG. 4
is a timing diagram showing the signal levels of FIG.
3
. With reference to
FIGS. 3 and 4
, the data receiver
20
using differential signaling has 2N data lines
11
,
13
, . . . ,
15
, and
17
that are used to receive 2N data, DATAi and /DATAi, where i is 1 through N. DATAi and /DATAi are complementary data.
If the voltage difference DD2 inputted to the data receiver
20
is the same as the voltage difference DD1 inputted to the data receiver
10
, the swing width of the data DATAi inputted to the data receiver
20
is reduced. As a result, the data receiver
20
can receive data at a high speed. However, the number of data lines of the data receiver
20
is N greater than that of the data receiver
10
using single reference signaling.
U.S. Pat. No. 6,160,423 discloses a high speed signaling technique. Because the trip-points of the two inverters of the receiver disclosed in detail in the '423 patent vary due to changes in a process, voltage, and temperature, the received data cannot be detected accurately. In addition, if levels of the output signals of comparators are low, it is difficult to detect the received data accurately.
Moreover, the receiver described in the '423 patent, which operates at a high frequency, cannot detect the received data accurately, and a glitch may occur during the switching operation of switches. Also, because the receiver described in the '423 patent uses an exclusive logical sum (XOR), the layout of the receiver requires more space.
SUMMARY OF THE INVENTION
In an exemplary embodiment, the present invention is directed to a data receiver and data receiving method that use signal integration to reduce high frequency noise.
In another exemplary embodiment, the present invention is directed to a data receiver and a data receiving method that is less sensitive to changes in a process, voltage, or temperature, and can detect data accurately and at high speed using two reference signal lines and a data line by differential signaling.
In another exemplary embodiment, the present invention is directed to a data receiver including an integration amplification circuit receiving at least two differential reference signals and N (where N is a natural number greater than zero) data signals and integrating and amplifying differences between the at least two differential reference signals and one or more of the N data signals and outputting at least first differential signals and at least second differential signals and a detection amplification circuit for receiving the at least first differential signals and the at least second differential signals and detecting a difference between the at least first differential signals and the at least second differential signals to detect a value of one or more of the N data signals.
In another exemplary embodiment, the present invention is directed to a data receiver including an integration amplification circuit for integrating and amplifying the difference between a first reference signal inputted through a first signal transmission line or the difference between a second reference signal inputted through a second signal transmission line and N (where N is a natural number greater than zero) data signals inputted through a third signal transmission line in response to a clock signal, and outputting at least first differential signals and at least second differential signals and a detection amplification circuit for receiving the at least first differential signals and the at least second differential signals and detecting a difference between the at least first differential signals and the at least second differential signals to detect a value of one or more of the N data signals.
In another exemplary embodiment, the present invention is directed to a data receiver including a first integration amplification circuit for integrating and amplifying the difference between a first of at least two reference signals and N (where N is a natural number greater than zero) data signals and outputting at least first differential signals in response to a clock signal, a second integration amplification circuit for integrating and amplifying the difference between a second of at least two reference signals and the N data signals and outputting at least second differential signals in response to the clock signal, and a detection amplification circuit for receiving the at least first differential signals and the at least second differential signals and detecting a difference between the at least first differential signals and the at least second differential signals to detect a value of one or more of the N data signals in response to the clock signal, wherein the first reference signal and the second reference signal of the at least two reference signals are differential signals.
In another exemplary embodiment, the first reference signal is inputted to a first input port of the first integration amplification circuit through a first signal transmission line, and the second reference signal is inputted to a first input port of the second integration amplification circuit through a second signal transmission line, wherein one or more of the N data signals is inputted to a second input port of each of the first integration amplification circuit and the second integration amplification circuit through a third signal transmission line.
In another exemplary embodiment, the first integration amplification circuit comprises a first precharge circuit for precharging the level of the at least first differential signals to the level of a first power voltage, in response to a first state of the clock signal and a first amplification circuit for integrating and amplifying the difference between the first of the at least two reference signals and one or more of the N data signals and outputting the at least first differential signals in response to a second state of the clock signal, wherein the second integration amplification circuit comprises a second precharge circuit for precharging the level of the at least two differential signals to the level of the first power voltage, in response to the first state of the clock signal and a second amplification circuit for integrating and amplifying the difference between the second of the at least two reference signals and one or more of the N data signals and outputting the at least sec
Harness & Dickey & Pierce P.L.C.
Wells Kenneth B.
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