Data reading path management architecture for a memory...

Details Data reading path management architecture for a memory... Data reading path management architecture for a memory...

1999-07-12

2001-04-03

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185170

Reexamination Certificate

active

06212096

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data reading path management architecture for a memory device, particularly of the non-volatile type.
2. Discussion of the Related Art
In a non-volatile memory, it is important to be able to provide architectures that perform data extraction as quickly as possible and in a reductive embodiment.
One of the solutions that is adopted most frequently is to associate a reference bit line with each bit of a word, so as to provide each selection line with a cell whose conductivity characteristics are fully similar to those of a generic virgin matrix cell, and at the same time, repeat the capacitive load of a corresponding bit line.
A drawback of this solution is the fact that it is not possible to repeat, in a simple way, the load of the entire selection path, such as for example a column multiplexer. Furthermore, the two selected cells (the matrix cell and the reference cell) are at a different distance from the same word line, with a consequent possible difference in signal level.
This drawback is lessened by using static sense amplifiers, in which one waits for the steady-state condition to be reached before proceeding with the reading operation. The use of these sense amplifiers, however, results in a waste of time for reading, since it is unable to dynamically lock the timing of the reading operation to the actual conductivity of a memory cell, i.e., to the signal level that is present therein.
On the other hand, the use of dynamic sense amplifiers is heavily penalized by the above mentioned drawback and by the additional inequality of the capacitive-resistive load of the lines. Furthermore, the architectures of conventional memory devices comprise, for redundancy management, redundancy line groups whose reference is constituted by the same reference columns used for the normal lines of the memory matrix.
In this manner, the redundancy bit lines are also compared with the corresponding reference lines, but if a bit is defective on a reference line, then the memory device is defective and must be rejected because it is impossible to change the reference, due to the presence of reference columns, one for each word bit of the memory.
SUMMARY OF THE INVENTION
One aim of the present invention is therefore to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that balances the read paths of the memory matrix side and of the reference side and the selection paths.
Within the scope of this aim, an object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows a reduced number of reference lines.
Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that detects the event of full propagation of a generic word line and at the same time assigns a corresponding reference cell to each bit line.
Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that achieves synchronous propagation of the signals on the lines and therefore both on the reference cells and on the matrix cells.
Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that enables and disables data transfer from the memory on a bus structure.
Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that provides redundancy even for any defective bits of the reference lines.
Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that produces paths for reproducing the normal propagation delays and paths within a memory matrix, for optimum balancing of the structure.
Another object of the present invention is to provide an architecture that is highly reliable and relatively easy to manufacture at competitive costs.
This aim, these objects, and others that will become apparent hereinafter are achieved by a data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means that are adapted to receive the data of the memory matrix for reading, characterized in that the memory matrix is divided into at least two half-matrices, each one of said two half-matrices having a reference line that is adapted to constitute a reference for reading the other half-matrix, the data sensing means receiving the data from one half-matrix and the reference from the other half-matrix, the data sensing means being adapted to transmit, according to a controlled timing, the data on an internal bus for their transmission from the memory matrix.
This aim, these objects, and others are furthermore achieved by a method for reading a memory device, particularly of the non-volatile type, that comprises at least two memory half-matrices, characterized in that it comprises the steps of:
precharging the two branches of data sensing means to their operating level, and equalizing said two branches so as to hold the data in the data sensing means in response to a pulsed read address transition signal;
producing a signal for disabling access to an internal bus for the transmission of the data of the memory device;
releasing the equalization of the two branches of the sense amplifier to allow transmission of the data of the at least two memory half-matrices; and
enabling the access of the data to the internal bus for the transmission of the data from the memory matrix.
According to another embodiment of the present invention, a system for balancing read paths of a memory device is disclosed, the system comprising first and second memory half matrices, each including a plurality of memory cells, data sensing means having a first input coupled to receive data from the first memory half-matrix and a second input coupled to receive data from the second half-matrix and means for selecting, when a memory cell of the first half-matrix is selected from reading, a corresponding memory cell of the second half-matrix. The selecting means comprises one reference line in each half-matrix, whereby, when one memory cell is selected in the first half-matrix for reading, the reference line of the second half-matrix activates a corresponding reference memory cell of the second half-matrix, thereby providing, to the data sensing means, data from the first half-matrix and a corresponding reference from the second half-matrix. The data sensing means comprises a plurality of sense amplifiers, each having a first output for transmitting data read from the first half-matrix to the internal bus, and a second output for transmitting data read from the second half-matrix to the internal bus. The system further comprises logic means for selecting one of the first and second outputs of each of the sense amplifiers and means for enabling and disabling access of the internal bus by the first and second outputs of each of the sense amplifiers. Each of the first and second half-matrices comprises redundancy lines, each of the first and second half-matrices are divided into a plurality of half matrix subsections that are driven by hierarchical decoding means. The number of data sensing means is equal to a number of word bits of word lines of the first and second half-matrices.


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European Search Report from European Patent Application 96830162.2, filed M

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