Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-08-21
2002-01-15
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210
Reexamination Certificate
active
06339548
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a data reading method in a semiconductor storage device for storing three- or multi-valued data in one memory cell.
BACKGROUND OF THE INVENTION
In a semiconductor storage device such as an EEPROM (Electrically Erasable Programmable Read Only Memory), or the like, put into practical use at present, no storage state but two kinds of storage states “0” and “1” can be set in one memory cell, so that the storage capacity of one memory cell is one bit (=two values). On the contrary, there has been proposed a semiconductor storage device in which four kinds of storage states “00” to “11” are set in one memory cell so that one memory cell has the storage capacity of two bits (=four values).
Such a semiconductor storage device as mentioned above (hereinafter referred to as “multi-valued memory”) will be described below referring to of an EEPROM as an example.
FIG. 6A
is a schematic sectional view of a floating gate type memory cell
61
in a conventional EEPROM. In this drawing, a drain
63
and a source
64
constituted by n-type impurity diffusion layers respectively are formed in a surface region of a p-type silicon substrate
62
so that a channel region
70
is formed between the drain
63
and the source
64
. Further, a bit line
65
formed by lamination and a source line
66
formed by lamination are electrically connected to the drain
63
and the source
64
, respectively. Further, a tunnel insulating film
71
constituted by an SiO
2
film having a thickness of about 10 nm is formed on the channel region
70
. A floating gate
67
constituted by low-resistance polysilicon, an interlayer insulating film
68
and a control gate (word line)
69
constituted by low-resistance polysilicon are formed successively on the tunnel insulating film
71
.
FIG. 6B
is a connection diagram of this memory cell.
A method of writing four-valued data “00” to “11” into the memory cell
61
formed as described above and reading the data from the memory cell
61
will be described below.
Firstly, the case of writing will be described. When, for example, data “11” is to be written into the memory cell
61
, the bit line
65
and the source line
66
are grounded and opened, respectively, and then a pulse voltage in a range of from about 10 v to about 15 V is applied to the control gate
69
. By application of the pulse voltage, a potential is induced in the floating gate
67
so that a predetermined quantity of electric charges are injected into the floating gate
67
by Fowler-Nordheim tunnelling in accordance with the potential difference between the floating gate
67
and the drain
63
. As a result, the threshold value of the gate voltage of the memory cell
61
increases to about 5 V. This state is defined as “11”. When, for example, data “10”, “01” or “00” is to be written into the memory cell, the threshold value of the gate voltage of the memory cell
61
can be set to be 3 V, 1 V or −1 V in the same manner as described above in the case of writing of data “11” while the voltage applied to the bit line
65
is selected to be 1 V, 2 V or 3 V.
Secondly, the case of reading will be described below. Generally, a field-effect transistor (FET) has such characteristic that a current flows across the source and drain of the FET if the voltage applied to the gate electrode of the FET is not lower than a threshold value in the case where a voltage is applied to the source or drain, while, on the contrary, no current flows across the source and drain of the FET if the voltage applied to the gate electrode of the FET is lower than the threshold value. Reading is executed by using this characteristic of the FET.
For example, a voltage of 1 V is applied to the bit line
65
, while the source line
66
is set to 0 V. In this condition, voltages of 0 V, 2 V and 4 V are applied to the control gate
69
successively. If a current flows across the source and the drain when a voltage of 0 V is applied to the control gate
69
, the threshold value of the gate voltage of the memory cell
61
is judged to be −1 V, and data “00” is therefore read out. On the other hand, if no current flows in the case of the gate voltage of 0 V but a current flows in the case of the gate voltage of 2 V, the threshold value of the gate voltage of the memory cell
61
is judged to be 1 V, and data “01” is therefore read out. Further, if no current flows in the case of the gate voltage of 0 V and in the case of the gate voltage of 2 V but a current flows first in the case of the gate voltage of 4 V, the threshold value of the gate voltage of the memory cell
61
is judged to be 3 V, and data “10” is therefore read out. Furthermore, if no current flows across the source and the drain in spite of the application of any of the above voltages to the control gate
69
, the threshold value of the gate voltage of the memory cell
61
is judged to be 5 V, and data “11” is therefore read out.
Although the above description has been made regarding where four-valued information, that is, two-bit information is stored in one memory cell, researches have been made upon the case where multi-valued information capable of indicating more values than four is stored in one memory cell.
In the aforementioned data reading method in the conventional multi-valued memory, however, there arises a problem that the number of times of reading operation subjected to one memory cell increases.
When, for example, four-valued information is stored in one memory cell, three times of reading operation in the gate voltage values of 0 V, 2 V and 4 V is required as described above. Although reading is practically performed while a voltage changed stepwise to be 0 V, 2 V and 4 V is applied to the control gate, the fact that three times reading operation is required remains unchanged.
When n-valued (n≧2) information is stored in one memory cell, (n−1) times of reading operation is generally required in the conventional reading method. In expression in the number of bits, when k-bit (k≧1) information is stored in one memory cell, (2
k
−1) times of reading operation is generally required in the conventional reading method.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a reading method in a semiconductor storage device in which the number of times of reading operation subjected to a multi-valued memory is reduced so that read access time can be shortened.
In order to attain the above object, according to an aspect of the present invention, a data reading method in a semiconductor storage device provided with at least one memory cell which has a control gate and an electric charge accumulating layer so that a threshold value of a gate voltage of the memory cell is controlled to be one V
th
(i) (in which i is an integer of 1 to n) of a number n (n≧3) of different values to thereby store three- or multi-valued information in one memory cell, comprises the steps of: applying a voltage V
1
represented by a relation V
th
(m
1
)≦V
1
<V
th
(m
1
+1) to the control gate of the memory cell to thereby detect whether a current flows across source and drain of the memory cell, where m
1
represents a maximum of integers not larger than n/2; applying a voltage V
2
represented by a relation V
th
(m
2
)≦V
2
<V
th
(m
2
+1) to the control gate of the memory cell to thereby detect whether a current flows across the source and drain of the memory cell when a current flows because of application of the voltage V
1
where m
2
represents a maximum of integers not larger than n/4; and applying a voltage V
3
represented by a relation V
th
(m
3
) ≦V
3
<V
th
(m
3
+1) to the control gate of the memory cell to thereby detect whether a current flows across the source and drain of the memory cell when no current flows in spite of application of the voltage V
1
, where m
3
represents a maximum of integers not larger than 3n/4.
Preferably, in the case of n=4 the method comprises the steps of: applying a voltage V
1
r
Connolly Bove & Lodge & Hutz LLP
Nippon Steel Corporation
Zarabian A.
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