Data read-out circuit for semiconductor memory device

Details Data read-out circuit for semiconductor memory device Data read-out circuit for semiconductor memory device

1992-04-20

1994-04-05

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 365210, 365208, G11C 1140

Patent

active

053011490

ABSTRACT:
A data read-out circuit in the semiconductor memory device has a sense circuit which detects the state of a selected memory cell and outputs a sense output voltage, a reference voltage generating circuit which outputs a reference voltage, and a comparison amplifier which compares the sense output voltage with the reference voltage and outputs an output voltage. The data read-out circuit further has a reference voltage control circuit consisting of a P-channel MOSFET connected between a power supply source and an output node of the reference voltage generating circuit. A gate of the P-channel MOSFET receives the sense output voltage from the sense circuit. When the sense output voltage is a low level, the P-channel MOSFET becomes conductive and the reference output voltage is changed to a high level substantially equal to the power supply voltage and, when the sense output voltage is a high level, the P-channel MOSFET becomes non-conductive and the reference output voltage is changed to a low level substantially equal to the ground potential. Therefore, the data read-out circuit has a wide operation margin and operates in low power consumption.

REFERENCES:
patent: 4799195 (1989-01-01), Iwahashi et al.
patent: 4802138 (1989-01-01), Shimamune
patent: 4916665 (1990-04-01), Atsumi et al.

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