Data read circuit for non volatile memory cells

Details Data read circuit for non volatile memory cells Data read circuit for non volatile memory cells

1999-10-06

2001-12-11

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210

Reexamination Certificate

active

06330188

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data read circuit for non volatile memory cells, organized in arrays, which provides an array branch comprising a bitline leading to a read cell apt to supply a cell current, a bias circuit for said bitline, a load circuit wherein is flowing an array current and which has, additionally, a reference branch including a bitline leading to a reference cell, which is apt to provide a virgin cell current, a bias circuit of said bitline, a load circuit wherein is flowing a reference current, means for unbalancing the array current with respect to the reference current.
BACKGROUND OF THE INVENTION
Reference herein will be made to conventional terms applying to MOS (Metal Oxide Semiconductor) transistors technology. In particular, the word ‘gate’ means the control or input electrode or control port of the MOS transistor, whereas ‘drain’ means the load or output electrode and ‘source’ the source or output electrode.
Non volatile memories are memories that do not loose their stored data when the circuit is no longer supplied. This kind of memories includes the following socalled ROM (Read Only Memory), EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), EAROM (Electrically Alterable Read Only Memory).
In EEPROM memories, in particular, the data to be stored is substantially stored inside a MOS transistor. Said MOS transistor has two gate electrodes, i.e. a control gate electrically connected to the circuit where the gate voltage is applied to, the other a so called floating gate separated by an SiO2 oxide barrier from the control gate, wherein it is buried. According to the logic status to be stored through application of proper voltages, an either positive or negative charge is trapped inside the floating gate. Said charge goes by tunnel effect from the substrate to the floating gate through the potential oxide barrier, where it remains trapped. The trapped charge influences the voltage-current feature of the transistor, with a consequent shift of the transistor threshold voltage according to the type of charge being trapped inside the floating gate. The cell consisting of the transistor may then take three different statuses, i.e. it can be written, cancelled or virgin, as to whether the floating gate contains either one or the other charge type or was never charged. Association between the logic status, the sign of the trapped charge and the programmation status of the cell, either written or cancelled, will be a matter of choice of most proper conventions and may change from product to product.
The logic status contained in the cell can be identified by detecting the current flowing through it under common bias conditions. In fact, if negative charges are trapped inside the floating gate, the transistor threshold voltage is higher compared to that of a virgin transistor, so for a same determined drain-source voltage the current will be lower. Viceversa, if positive charges are trapped in the floating gate, the threshold voltage will decrease compared to a virgin transistor and the current be higher.
A logical status is in fact detected by comparing a cell current with the current of a virgin cell under the same bias conditions. Such a comparison is made through a ‘sense amplifier’ or read amplifier.
Several circuit techniques are available, which tend to the construction of a reference circuit for the sense amplifier to safely devise between the current associated to a virgin cell and the current associated to a programmed cell.
FIG. 1
shows a circuit diagram of a read circuit for memory cells
1
in a non volatile memory according to the known state of the art. Said read circuit of memory cells
1
consists of two substantially symmetric branches, i.e. a left branch
2
and a right branch
2
′. The left branch
2
comprises a left array of memory cells
3
, a selection circuit of the memory cells
4
operating on a bitline BL, a bias circuit
5
, a load circuit
6
, whereas the right branch
2
′ comprises a right array of memory cells
3
′, a selection circuit of the memory cells
4
′ operating on a bitline BL′, a bias circuit
5
′, a load circuit
6
′.
Both the load circuit
6
and load circuit
6
′ consist of their relevant MOS p-channel transistors M
1
and M
1
′, which are joined together in a current-mirror or current repeater configuration, while input terminals IN and IN′ of a differential amplifier not shown here are connected to their drain nodes, which are defined as nodes D and D′, respectively.
The bias circuit
5
is used to set a fixed voltage value during read operation, which essentially consists of an n-channel pass transistor M
2
, whose control electrode or ‘gate’ is driven by an inverter circuit, obtained in this case through a NOR logical gate
7
having one input connected to the bitline BL. The other input of the logical gate
7
will receive an enable signal EN. The bias circuit
5
is usually called a “cascode circuit”.
The selection circuit of memory cells
4
is a transistors circuit receiving at its input the address signals for selecting the memory cells to be read contained in the left array of memory cells
3
. Operation of the circuits pertaining to the right branch
3
′ are not further described here, as it is analogous.
The left array of memory cells
3
and the right array of memory cells
3
′ usually contain reference cells, which are still virgin and can be employed as a reference for the sense amplifier when reading the dual array of memory cells. In
FIG. 1
the right branch
2
′ operates as a reference branch, so that a virgin cell current Iv is flowing in the reference cell REF′ belonging to the right array of memory cells
3
′. Therefore, the selected cell contained in the left array of memory cells
3
is a standard memory cell C supplying a cell current Ic, even if the left array of memory cells
3
may also contain reference cells itself.
It will be appreciated that in order to provide a safe detection, the load circuit
6
′ comprises a MOS p-channel transistor M
3
′, which is installed in parallel to the transistor M
1
′ of which it has the same aspect ratio. The function of such a transistor M
3
′ is to cause a loads unbalance in the read circuit of the memory cells
1
, so that a current I will flow in the left branch
2
, which is a half of a current I′ flowing in the right branch
2
′, causing a further voltage unbalance on nodes D and D′, i.e. on input terminals IN and IN′ of the differential amplifier, so allowing for a correct data reading in the memory cell. The read circuit of memory cells
1
will thus set a current value in the reference branch, whose ratio with the array current is proportional to the loads ratio.
Such a circuit has the following drawbacks. First of all, a poor symmetry of the circuits connected to the input terminals of the sense amplifier. Symmetry condition is particularly important when using dynamic amplifiers with a latch structure. Moreover, the difference between current I and current I′ can be at most half the current supplied by the reference branch.
Finally, said circuit has high implementation difficulties whenever an exchange should be made between the branch with the reference function and the branch with an array function.
It is also known to use a symmetric loads circuit instead of the loads unbalance method, as it provides for injection of an offset-current on the array branch through a proper current source. The injection node is usually the one on the bitline, between the selection circuit and bias circuit. However, such a circuit involving execution of current sources based on current mirrors placed at a certain distance from the bitlines will cause some difficulties in the bias diffusion of the bitline, which is particularly undesired as it damages a correct data reading, in particular for dynamic approaches. Moreover, introduc

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