Facsimile and static presentation processing – Static presentation processing – Memory
Reexamination Certificate
1998-02-24
2002-04-16
Nguyen, Madeleine (Department: 2622)
Facsimile and static presentation processing
Static presentation processing
Memory
C358S001180, C358S474000
Reexamination Certificate
active
06373589
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data read apparatus and method capable of reading a variety of data which is stored in a buffer configured with DRAM and necessary for recording, and a printing apparatus.
Recently, as the print speed and dot density produced by printing apparatus when printing characters have increased, the amount of print data read from a print buffer of a printing apparatus per unit time has also increased. For this reason, it becomes necessary to access DRAM configuring the print buffer at high speed. One method for realizing high-speed access DRAM is a hyper-page mode access. Generally, the memory location of DRAM to be accessed is specified by a row address and a column address based on an address generated by, e.g., a CPU. The hyper-page mode is for realizing the high-speed reading and writing of data from/to DRAM by fixing the row address while changing the column address of the DRAM at high speed. In a case of accessing a print buffer configured with DRAM in the hyper-page mode, data can be continuously read as long as the row address does not change. Therefore, it is possible to continuously access a print buffer to read the necessary number of data (n data) when all the n data are stored at the same row address locations. However, in a case where the row address changes during reading of the n data, x number of data (x data) are continuously read before the row address changes. Thereafter, the row address is changed and the rest of the n data (n−x data) are read.
However, in the hyper-page mode for accessing DRAM at high speed, when a changing point of row address is found while accessing of the DRAM, it is not possible to stop accessing DRAM immediately. Accordingly, in a case where the row address has to be changed while reading the n data in the hyper-page mode, it is necessary to determine timing to issue a request for terminating the access in the current row in consideration of the addresses (unnecessarily read addresses) to which the access has proceeded before the access to the DRAM is actually stopped once the termination of access is requested. Therefore, a processing circuit for determining the changing point of row address is necessary. Furthermore, in a case where the number of addresses between an address where access starts and a changing point of row address is equal or less than the number of unnecessarily read addresses, it is even impossible to start accessing in the hyper-page mode, and thus access to DRAM has to be performed in normal mode, which makes the processing complicated.
There is a method for determining an access pattern by finding a changing point of the row address before starting accessing DRAM. In such cases, it is necessary to find the changing point of row address by sequentially comparing all the addresses to be accessed by a pair of addresses generated successively in advance, which requires an extra circuit and a long processing time. When reading the n data, a possible changing point of row address is at one of (n−1) points at maximum. Therefore, in a case where the row address changes at most one time while reading the n data, there are n different access patterns depending upon the position of a changing point, which requires n types of controllers corresponding to the number of the access patterns.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to simplify necessary processes while accessing of DRAM by omitting control for determining row address change during accessing DRAM and terminating the access, and control for determining a changing point of row address before starting accessing the DRAM and selecting an access pattern depending upon the determination result, further, omitting a circuit which was necessary for processes performed before starting accessing the DRAM, and circuits which were necessary for complicated control during processing time and during accessing the DRAM.
According to the present invention, the foregoing object is attained by providing a data read apparatus for reading data from memory of which location to be accessed is specified by a row address and a column address on the basis of a designated address. In one embodiment, a reading means reads a predetermined number of data by changing the column address while fixing the row address, starting from a designated start address of the memory. If a location to be read has a change in row address, that fact is detected. A storage means is provided for storing data read by the reading means until either a change in row address is detected or the number of stored data reaches the predetermined number. In a case where the change in row address is detected, an address whose row address is changed is used as the start address, and reading of data by the reading means and storing of the read data to the storage means are repeated.
Further, the foregoing object is also attained by providing a similar data read method.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.
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