Data rate limiting

Details Data rate limiting Data rate limiting

2005-09-06

2005-09-06

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C709S241000

Reexamination Certificate

active

06940861

ABSTRACT:
A packetized-data processing apparatus includes a memory configured to store core groups of packetized data, a channel coupled to the memory and having a total bandwidth for transferring packets of data from the core groups, and a scheduler operatively coupled to the memory and the channel and configured to allocate amounts of the total bandwidth of the channel to each of the core groups that is backlogged, while limiting the amount of allocated bandwidth, and a corresponding transfer rate of packets of data, for each core group to a maximum allowable bandwidth for each core group, to schedule transfer of packetized data of the core groups from the memory to the channel in accordance with the respective amounts of allocated bandwidth for the core groups.

REFERENCES:
patent: 5463620 (1995-10-01), Sriram
patent: 6067301 (2000-05-01), Aatresh
patent: 6452933 (2002-09-01), Duffield et al.
patent: 0901301 (1999-10-01), None
patent: 0977405 (2000-02-01), None
Altintas et al., A Note on Fair Queueing and Best-Effort Service in the Internet, IEEE 0-7803-9939-0/99, 1999.
Notification of Transmittal of The International Search Report or the Declaration, mailed Nov. 19, 2001.

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