1994-12-28
1997-07-15
Harrell, Robert B.
G06F 501, G06F 1300
Patent
active
056491190
ABSTRACT:
A plurality of shift memories shifting data are connected in series, destination indicating bits indicative of data destination are stored in destination indicating bit memories corresponding to the shift memories respectively, and a searching circuit is provided adjacent to each of the destination indicating bit memories, which searching circuit searches data by searching the destination indicating bits.
REFERENCES:
patent: 4603416 (1986-07-01), Servel et al.
patent: 5504741 (1996-04-01), Yamanaka et al.
"An Asynchronous Time-Division Switched Network", by J. P. Coudreuse et al., International Conference on Communication, 1987, Session 22.
"New Address-Queueing Architecture for a Shared-Buffering Type ATM Switch", H. Yamanaka et al., proceedings of the 1993 IEICE Fall Conference.
"An Elastic Pipeline Mechanism by Self-Timed Circuits", IEEE Journal of Solid-State Circuits, vol. 23, No. 1.
Ishiwaki Masahiko
Kondoh Harufusa
Notani Hiromi
Yamanaka Hideaki
Harrell Robert B.
Mitsubishi Denki & Kabushiki Kaisha
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