Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-02
2001-02-27
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185160, C365S185030
Reexamination Certificate
active
06195287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multilevel programming method for a semiconductor storage, in particular, for floating gate nonvolatile semiconductor storage of a virtual ground memory array.
2. Description of the Prior Art
In recent years, virtual ground type flash memory devices aiming for high packing density have drawn attention, such as for example, ‘A New Cell Structure for Sub-quarter Micron High Density Flash Memory’ (IEDM Technical Digest, pp.269-270, 1995), and an ACT (Asymmetrical Contactless Transistor) type flash memory disclosed in ‘An investigation of a sensing method of an ACT type flash memory’ (ICD97-21, p.37, 1997, a technical report of The Institute of Electronics, Information and Communication Engineers).
In such an ACT type flash memory, programming (writing) and erasing operations are implemented based on the FN tunnel effect, and it is expected that it will be used for data storage.
Referring now to
FIGS. 1 and 2
, this ACT type flash memory will be described.
An ACT type flash memory uses the FN tunnel effect when programming and erasing as stated above, and has a virtual ground array configuration in which each bit line is shared between two memory cells. In such an ACT type flash memory, the bit lines are shared and formed of a diffusion layer to thereby reduce the number of contacts and enable a remarkable reduction of the array area, which leads to high integration.
Next, an ACT type flash memory device, as sectionally shown in
FIGS. 2A and 2B
, has, in order from the top, a control gate WL, an inter-layer insulating layer, a floating gate FG and a bit line (diffusion layer) arranged in a layered manner. The common bit line formed under and between the adjacent floating gates FG has different donor densities between the drain and source sides.
In
FIG. 1
where ACT type flash memory cells are arranged in an arrayed configuration, MBLX represents a main bit line, SBLx represent a sub-bit line formed of a diffusion layer, WLx represents a word line, SGx represents a select gate selection signal line, CONTACT represents a contact point between a main bit line and a sub-bit line (belonging to different layers). Here, x represents an integer ranging from 0 to n.
Next, programming and erasing operations for an ACT type flash memory using the FN tunnel effect will be described.
First, programming the ACT type flash memory (see
FIG. 2A
) is performed with a negative voltage of −8 (v) applied to the control gate i.e., word line WL and a positive voltage of 5 (v) applied to the drain side. By this voltage application, the FN tunnel effect occurs on the drain side so that electrons are extracted from floating gate FG to the drain side. This extraction lowers the threshold voltage, thus implementing programming. Here, word line WL is also referred to as control gate WL.
An erase operation is performed with a high voltage of 10 (v) applied to control gate WL and a negative voltage of −8 (v) applied to a bit line BL and the substrate
109
(P-portion) so as to generate the FN tunnel effect between the channel layer (channel) and floating gate FG to thereby inject electrons into the floating gate FG. This injection of electrons raises the threshold voltage, which means that erasing is implemented.
A more detailed operation will be described based on the basic configuration of one memory cell M schematically shown in FIG.
3
.
To begin with, for a program operation, or to extract electrons from floating gate FG, a negative voltage Vnw (−8 (v)) is applied to control gate WL, a positive voltage Vpp (+5 (v)) is applied to drain
105
and source
107
is set floating. Under these conditions, electrons are drawn from floating gate FG by the FN tunnel effect, and thereby the threshold voltage of memory cell M is lowered to about 1.5 (v).
For an erase operation, or to inject electrons into floating gate FG, a positive voltage Vpe (+10 (v)) is applied to control gate WL, a negative voltage Vns (−8 (v)) is applied to source
107
and drain
105
is set floating. Under these conditions electrons are injected into floating gate FG by the FN tunnel effect and thereby the threshold voltage of memory cell M is raised over about 4 (v).
A flash memory as above which uses the FN tunnel effect for both program and erase operations is called an FN-FN operating flash memory.
For a read operation, 3 (v) is applied to control gate WL, 1 (v) is applied to drain
105
, 0 (v) is applied to source
107
. The current flowing through cell M under the conditions, is detected by an unillustrated sensing circuit to read out the data.
The application of voltage for the above operations is summarized in Table 1.
TABLE 1
Application of voltage to a conventional flash memory
Control Gate
Drain
Source
P-type Well
Program
−8 V
5 V
Open
0 V
Erase
10 V
Open
−8 V
−8 V
Read
3 V
1 V
0 V
0 V
Here, the values shown in Table 1 are voltages to be applied to a selected memory cell M.
In the field of memory technology, as an attempt to aim at higher integration, multilevel techniques for introducing three or more threshold levels to each memory cell M have been published.
The examples include the methods disclosed in 1996 ISSCC Dig. Tech. Papers, pp36-37 “A 98 mm
2
3.3V 64 Mb-Flash Memory with FN-NOR Type-4level cell” and in Japanese Patent Application Laid-Open Hei 6 No.177397.
In these methods, an FN-NOR type flash memory is used. Programming pulses for data ‘
11
’, ‘
10
’ and ‘
01
’ are simultaneously applied by applying different voltages to drains
105
with respect to each data, making use of the cell characteristics shown in FIG.
4
. Based on these characteristics, memory cell M is programmed so as to have a voltage falling within one of the threshold voltages in the distribution shown in FIG.
5
.
As shown in
FIG. 5
, data ‘
00
’ is the erased state.
Subsequently, a verify operation (data verification after programming) is performed in two stages.
At the first stage, the reference voltage Ref (the standard voltage with which comparison is made) is set at around 2.3 (v), for example, so as to judge whether the threshold voltage falls within the ‘
11
’ and ‘
10
’ states or within the ‘
01
’ and ‘
00
’ states shown in FIG.
5
.
Next, at the second stage, a different operation as follows will be effected based on the sensed result from the first stage.
When the sensed result from the first stage falls within the ‘
11
’ or ‘
10
’ state, then the reference voltage Ref is set at 1.3 (v), for example, so as to determine whether the level is ‘
11
’ or ‘
10
’.
When the sensed result from the first stage falls within the ‘
01
’ or ‘
00
’ state, then the reference voltage Ref is set at around 3.3 (v), for example, so as to determine whether the level is ‘
01
’ or ‘
00
’.
The above operations, that is, application of the programming pulses are repeated based on the verification result until the desired threshold voltage is obtained. Generally, the characteristics fluctuate when the FN tunnel effect is used, so that a pulse width shorter than that meeting the actual characteristic is used. That is, pulse applications (voltage application to drain
105
) are stopped in the order in which programming is completed, so as to set the designated threshold voltages whilst preventing the lowering of the threshold voltages.
Next, description will be made of a case where the four-level programming method used in the aforementioned FN-NOR type flash memory is applied to a virtual ground ACT type flash memory.
FIG. 6
shows a flowchart of the programming algorithm of this case.
With the selected word line (WL) set at −8 (v), pulses of voltage corresponding to the data for individual cells M which are to be programmed with data ‘
11
’, ‘
10
’ or ‘
01
’ are applied simultaneously to respective drains
105
of the cells M as the drain voltage (Vd) so as to effect data writing (Step S11).
As the drain voltage Vd, 6 (v) is applied to the drains of cells M which are to be programmed with data ‘
11
Elms Richard
Morrison & Foerster / LLP
Nguyen Tuan T.
Sharp Kabushiki Kaisha
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