Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-04
2003-05-20
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S203000, C365S230060
Reexamination Certificate
active
06567314
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories and in particular to non-volatile floating gate and MONOS memories.
2. Description of the Related Art
A conventional two poly planar floating gate device structure is shown in FIG.
1
. The word select gate
10
is a polysilicon gate stacked above a floating gate
11
, which is also polysilicon. Two diffusions form the source
13
and drain
12
. In order to program the memory cell, electrons must cross the oxide barrier into the floating gate
11
. There are two main mechanisms for program, Channel Hot Electron injection (CHE) and Fowler-Nordheim tunneling (FN). Typical CHE voltages are as follows: The word gate
10
is biased to 11 V, and the program drain
12
is biased to 8V. The voltage of source diffusion
13
is grounded. In this device structure, CHE requires a high drain to source voltage and is characterized by program currents of greater than 100 uA per cell. Program data widths are usually limited to 8, 16 or 32 bits because of high voltage charge pump constraints.
In Fowler-Nordheim tunneling program, the word gate
10
is usually biased to a high voltage of 20V, and both the source
13
and drain
12
are grounded. Program currents are on the order of 10 nA/cell, so all cells sharing a single word line and can be selected and programmed together without needing a high current charge pump. For a conventional NAND array device that utilizes FN program, a page buffer is usually implemented in which there exists one program data latch for each bit diffusion line. The cells on a word line which are not to be programmed to a high threshold “0” state need to be program inhibited. Implementation of the page buffer presents a layout challenge and significant area penalty.
An implementation of program data latches in a page buffer is described in “A Dual Page Programming Scheme for High Speed Multi-Gb-Scale NAND Flash Memories”, by Ken Takeuchi and TomoharuTanaka, IEEE 2000 Symposium on VLSI Circuits Digest of Technical Papers, June 2000, pp 156-157. In this paper, two memory blocks share one page buffer, by taking advantage of the zero drain to source current during FN program. Bit line leakage was shown to be less than 0.1 mV. The values of the data latches could be coupled to the bit lines of one block and then safely floated, during program. The same data latches could then be used to program a second block, at the same time, reducing the number of data latches needed by half. However, this particular configuration could only be used by FN program, because the non-zero drainsource current in CHE program will not allow for floating bit lines.
In U.S. Pat. No. 6,275,415 B1 (Haddad et al) a memory device is directed to having multiple memory cells with a method of programming multiple memory cells wherein a bias voltage is applied to a common source terminal and a time varying voltage is applied to gates of cells to be programmed and using channel hot electrons (CHE). U.S. Pat. No. 5,753,951 (Geissler) is directed to CHE injection techniques where the memory cell has a floating gate structure that extends over a sharp edge of a memory cell trench and then into the trench. U.S. Pat. No. 5,874,337 (Geissler) is directed toward the method of creating a memory cell with a floating gate structure that extends over and into a memory cell ctiewzw trench. U.S. Pat. No. 6,166,410 (Lin et al.) is directed to a structure and method of manufacture of a split gate MONOS memory device having a MONOS transistor in series with a stacked polysilicon gate flash transistor.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a new method for writing data using CHE programming for non-volatile floating gate and MONOS memories.
Another objective of the present invention is to provide a new circuit to handle write data during CHE programming.
Yet another objective of the present invention is to provide a bit line precharge to inhibit all memory cells before a selective bit line discharge is done to program selected memory cells.
A further objective of the present invention is to reduce the number of sense amplifiers and write data circuits to be equal to the program data width.
Again a further objective of the present invention is to produce a write data circuit that is constructed with logic transistors.
Again a further objective of the present invention is to simplify circuitry required to write data for non-volatile floating gate and MONOS memories.
Still a further objective is to selectively precharge bit lines for low power and low current operations.
Yet a further objective of the present invention is produce circuit area savings through reduction in the complexity of circuitry associated with writing data to nonvolatile floating gate and MONOS memories.
Still yet a further objective of the present invention is to reduce the oxide thickness of decode transistors and reduce high voltage transistors.
A new method and circuit to handle write data during CHE program is described in the present invention. A sequence of first precharging memory bit lines and then discharging the bit lines is used to program selected memory cells. A bit line precharge is first implemented to program inhibit all memory cells, and then a selective bit line discharge is done to program selected memory cells. The number of data latches needed is reduced to the actual program data width resulting in significant area savings and circuit simplification.
REFERENCES:
patent: 5753951 (1998-05-01), Geissler
patent: 5874337 (1999-02-01), Geissler
patent: 5886927 (1999-03-01), Takeuchi
patent: 6049899 (2000-04-01), Auclair et al.
patent: 6166410 (2000-12-01), Lin et al.
patent: 6243297 (2001-06-01), Nagatomo
patent: 6275415 (2001-08-01), Haddad et al.
patent: 6288941 (2001-09-01), Seki et al.
patent: 6345000 (2002-02-01), Wong et al.
patent: 6426894 (2002-07-01), Hirano
“A Dual Page Programming Scheme for High Speed Multi-Gb-Scale NAND Flash Memories,” by Ken Takeuchi et al., IEEE 2000 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2000, pp. 156-157.
Ogura Seiki
Ogura Tomoko
Ackerman Stephen B.
Halo Lsi, Inc.
Le Thong
Saile George O.
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