Data processor with serially accessed set associative memory cac

Details Data processor with serially accessed set associative memory cac Data processor with serially accessed set associative memory cac

Filed on

1994-09-06

Date issued

1997-06-03

Examiner

Moore, David K.

Other Related Categories

395467, 395496, G06F 1208

Type

Patent

Status

active

Patent number

056363540

Description

ABSTRACT:
A memory cache interface (12) serially accesses each way in an M-way set asociative memory cache (11) when it performs a read operation. The memory cache returns a data quantum and a tag corresponding to each presented input. The memory cache interface presents a portion of a main memory address and a new value of a way signal to the memory cache until it finds a match between the output tag and the remainder of the main memory address. The memory cache interface allows set-associative caches to be constructed from simple memory blocks for use with devices in which the memory cache interface may be incorporated. The memory cache interface may be incorporated into such devices as data processors and microcontrollers.

REFERENCES:
patent: 5113506 (1992-05-01), Moussouris et al.
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5325507 (1994-06-01), Freitas et al.
patent: 5345576 (1994-09-01), Lee et al.

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