Data processor with selectively enabled and disabled branch pred

Details Data processor with selectively enabled and disabled branch pred Data processor with selectively enabled and disabled branch pred

1991-03-06

1993-07-13

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 36494834, 364938, 3642318, 3642613, G06F 938, G06F 932

Patent

active

052281310

ABSTRACT:
The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register. Likewise, when the reliability of the branch history lowers due to such as variation in the program running condition, the data processor is capable of clearing the branch history by writing a specific value into the exclusive usable register, and when executing a specific instruction which varies the program executing condition, branch history is automatically cleared.

REFERENCES:
patent: 4477872 (1984-10-01), Losq et al.
patent: 4760520 (1988-07-01), Shintani et al.
patent: 4763245 (1988-08-01), Emma et al.
patent: 4764861 (1988-08-01), Shibuya
patent: 4777594 (1988-10-01), Jones et al.
patent: 4827402 (1989-05-01), Wada
patent: 4853840 (1989-08-01), Shibuya
patent: 4858104 (1989-08-01), Matsuo et al.
"Branch Prediction Strategies and Branch Target Buffer Design," Lee, et al, Computer, vol. 17, No. 1, Jan. 1984.

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