Data processor with rename buffer and FIFO buffer for in-order i

Details Data processor with rename buffer and FIFO buffer for in-order i Data processor with rename buffer and FIFO buffer for in-order i

1995-05-17

1996-03-19

Lim, Krisna

Boots, shoes, and leggings

3642318, G06F 930

Patent

active

055009433

ABSTRACT:
A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.

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Diffendorff et al; "Organization of the Motorola 881/0 Superscaler RISC Microprocessor", IEEE Micro, vol. 12, No. 2, Apr. 1992 pp. 40-63.

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