Data processor with R/W memory write inhibit signal

Details Data processor with R/W memory write inhibit signal Data processor with R/W memory write inhibit signal

1982-04-19

1984-11-27

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

044854560

ABSTRACT:
A main power source voltage is compared with a reference voltage, when the main power voltage drops lower than the reference voltage, an operation/halt signal is formed, a read/write memory write inhibit signal is formed in response to the operation/halt signal, and the read/write memory is inhibited in operation. This write inhibit signal is formed by setting a D-type latch at the timing of the transition of the NIF signal to active mode.

REFERENCES:
patent: 3911406 (1975-10-01), McLaughlin et al.
patent: 4328558 (1982-05-01), Musa et al.
patent: 4387442 (1983-06-01), Stuehler
Motorola Semiconductors, Advance Information ADI-803R2, p. 20.
National Semiconductor 48-Series, Microcomputers Handbook 1980, pp. 2-19 and 2-20.

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