Data processor with quicker latch input timing of valid data

Details Data processor with quicker latch input timing of valid data Data processor with quicker latch input timing of valid data

1993-10-27

1995-11-28

Geckil, Mehmet

Boots, shoes, and leggings

364DIG1, 364265, 3642663, G06F 1100

Patent

active

054716306

ABSTRACT:
A data processing apparatus includes a first data holding circuit, a second data holding circuit, a signal processing circuit, and a control circuit. The first data holding circuit outputs a signal as three values data representing a first valid value having a first logic value, a second valid value having a second logic value, and an invalid value. The second data holding circuit holds the three values data from the first data holding circuit. The signal processing circuit receives the three values data from the second data holding circuit and outputs a first ready signal indicating completion of data processing. The control circuit controls the second data holding circuit to hold the three values data from the first data holding circuit, and also outputs a second signal indicating completion of data processing in the second data holding circuit to the first data holding circuit when the three values data from the first data holding circuit exhibits one of the first and second valid values and the first ready signal is input from the signal processing circuit.

REFERENCES:
patent: Re33739 (1991-11-01), Takashima et al.
patent: 3641327 (1972-02-01), Nelson, Jr.
patent: 3961250 (1976-06-01), Snethen
patent: 5051911 (1991-09-01), Kimura et al.

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