Data processor with plural instruction execution parts for synch

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3642295, 364230, 3642306, 3642405, 36424293, 3642624, 3642628, 364263, 3642633, 3642623, 3642684, 364DIG1, 364DIG2, G06F 926, G06F 930, G06F 938

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054045576

ABSTRACT:
A data processor with plural instruction execution parts for synchronized parallel processing which generates first information indicating the order of each group of instructions having successive instruction addresses and second information indicating the order of each instruction in each group of instructions, which feeds both information to any one of instruction execution parts so that such information is added to respective corresponding instructions. The address control part holds the address of a first instruction of each group of instructions so that an instruction address to be saved can be derived when an exception occurs. Only a first instruction of a first group of instructions is allowed to complete its execution in the instruction execution parts. The first information is updated together with the second information every time the execution of one instruction is completed. The supply of next instructions is brought to a stop on the detection of the occurrence of an exception. Each instruction execution part invalidates, at the time that the executions of all instructions fed earlier than an instruction that has detected the occurrence is complete, the processing of remaining instructions. Thus, the synchronization of one instruction execution with the other, the saving of an instruction address when an exception occurs, and the invalidation of instruction processing can all be realized, with less hardware.

REFERENCES:
patent: 4001788 (1977-01-01), Patterson et al.
patent: 5241633 (1993-08-01), Nishi
patent: 5247628 (1993-09-01), Grohoski
patent: 5280615 (1994-01-01), Church et al.
U.S. Ser. No. 07/580,718 filed Sep. 11, 1990, Edamatsu.
U.S. Ser. No. 07/861,327 filed Mar. 31, 1992, Yamashita.

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