Data processor with pipeline which disables exception processing

Details Data processor with pipeline which disables exception processing Data processor with pipeline which disables exception processing

1989-02-17

1993-03-09

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 3642318, 3642613, 3642619, 395800, G06F 938

Patent

active

051931567

ABSTRACT:
The data processor of this invention is provided with a multi-stage pipeline processing mechanism which predicts the probability of the branch instruction branching at the instruction decoding stage. The mechanism also detects exceptions at pre-branching and transmits information about a detected exception to the instruction execution stage. If, at the execution stage, it is determined that the branch prediction was incorrect, exception processing is not started. If, at the execution stage, it is determined that the branch prediction was correct, exception processing is started. In this way it is possible to reduce disturbances in pipeline processing for many branch instructions.

REFERENCES:
patent: 4435756 (1984-03-01), Potush
patent: 4477872 (1984-10-01), Losq et al.
"Branch Prediction Strategies and Branch Target Buffer Design," Lee, et al, Computer, vol. 17, No. 1, Jan. 1984.
"Reducing the Cost of Branches," McFarling, et al, The 13th Annual International Symposium on Computer Architecture, Jun. '86.

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