Data processor with operation units executing dyadic and monadic

Details Data processor with operation units executing dyadic and monadic Data processor with operation units executing dyadic and monadic

1995-12-13

1997-03-18

Kim, Matthew M.

395476, G06F 1500, G06F 1200

Patent

active

056131526

ABSTRACT:
A data processor of modular architecture comprises a plurality of operation units, each serving to implement specific functionalities as required by the instruction set that determines the processor's operation. Register files for several ones among the operation units are merged. At least one of the register files is exclusively assigned to one of the operation units. At the expense of only a marginal increase, if any, of the number of instruction cycles, smaller register file areas in an IC embodiment, less register file control circuitry and simpler microcode words are obtained.

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