Data processor with on-chip logical addressing and off-chip phys

Details Data processor with on-chip logical addressing and off-chip phys Data processor with on-chip logical addressing and off-chip phys

1990-10-12

1992-07-07

Bowler, Alyssa H.

G06F 906, G06F 1300, G06F 9312

Patent

active

051290758

ABSTRACT:
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction. The instruction execution unit uses operand data read out from the second associative memory when the operand data is present in the second associative memory and operand data from the main memory when the operand data is not present in the second associative memory.

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