Data processor with dynamic and selectable interconnections betw

Details Data processor with dynamic and selectable interconnections betw Data processor with dynamic and selectable interconnections betw

1995-12-15

1998-11-03

Bowler, Alyssa H.

Boots, shoes, and leggings

39580014, 39580018, 364243, 3642457, 3642544, 364DIG1, G06F 1300

Patent

active

058322914

ABSTRACT:
A data processor intended for a single instruction, multiple data mode operation includes memory that is external to the processor array, and a controller that dynamically and selectably interconnects multiple edges of the processor array with the memory and with I/O ports. A separate controller module is provided for each memory channel, and interconnects with corresponding edge processing elements of the processor array. The controller modules for the different channels are independent of each other, as are the channel memories. In the case of a rectangular processor array, each channel memory can be implemented with only three memory stores that are interconnected with the four edges of the processing array and the I/O ports through the channel controller module, yet for most algorithms provide a throughput that is comparable to that resulting from the use of four memory stores.

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"The Distributed Array of Processors (DAP)," Parallel Supercomputing in SIMD Architectures, Chapter 5, pp. 143-164, 1990, CRC Press Inc.

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